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![Tony Lindgren](/assets/img/avatar_default.png)
Based on earlier discussions[1] we attempted to find a suitable
location for the omap DMA header in commit 2b6c4e73
(ARM: OMAP:
DMA: Move plat/dma.h to plat-omap/dma-omap.h) until the conversion
to dmaengine is complete.
Unfortunately that was before I was able to try to test compile
of the ARM multiplatform builds for omap2+, and the end result
was not very good.
So I'm creating yet another all over the place patch to cut the
last dependency for building omap2+ for ARM multiplatform. After
this, we have finally removed the driver dependencies to the
arch/arm code, except for few drivers that are being worked on.
The other option was to make the <plat-omap/dma-omap.h> path
to work, but we'd have to add some new header directory to for
multiplatform builds.
Or we would have to manually include arch/arm/plat-omap/include
again from arch/arm/Makefile for omap2+.
Neither of these alternatives sound appealing as they will
likely lead addition of various other headers exposed to the
drivers, which we want to avoid for the multiplatform kernels.
Since we already have a minimal include/linux/omap-dma.h,
let's just use that instead and add a note to it to not
use the custom omap DMA functions any longer where possible.
Note that converting omap DMA to dmaengine depends on
dmaengine supporting automatically incrementing the FIFO
address at the device end, and converting all the remaining
legacy drivers. So it's going to be few more merge windows.
[1] https://patchwork.kernel.org/patch/1519591/#
cc: Russell King <linux@arm.linux.org.uk>
cc: Kevin Hilman <khilman@ti.com>
cc: "Benoît Cousson" <b-cousson@ti.com>
cc: Herbert Xu <herbert@gondor.apana.org.au>
cc: "David S. Miller" <davem@davemloft.net>
cc: Vinod Koul <vinod.koul@intel.com>
cc: Dan Williams <djbw@fb.com>
cc: Mauro Carvalho Chehab <mchehab@infradead.org>
cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
cc: David Woodhouse <dwmw2@infradead.org>
cc: Kyungmin Park <kyungmin.park@samsung.com>
cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
cc: Hans Verkuil <hans.verkuil@cisco.com>
cc: Vaibhav Hiremath <hvaibhav@ti.com>
cc: Lokesh Vutla <lokeshvutla@ti.com>
cc: Rusty Russell <rusty@rustcorp.com.au>
cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
cc: Afzal Mohammed <afzal@ti.com>
cc: linux-crypto@vger.kernel.org
cc: linux-media@vger.kernel.org
cc: linux-mtd@lists.infradead.org
cc: linux-usb@vger.kernel.org
cc: linux-fbdev@vger.kernel.org
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
957 lines
22 KiB
C
957 lines
22 KiB
C
/*
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* Cryptographic API.
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*
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* Support for OMAP AES HW acceleration.
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*
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* Copyright (c) 2010 Nokia Corporation
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* Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/crypto.h>
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#include <linux/interrupt.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/aes.h>
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#include <linux/omap-dma.h>
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/* OMAP TRM gives bitfields as start:end, where start is the higher bit
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number. For example 7:0 */
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#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
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#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
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#define AES_REG_KEY(x) (0x1C - ((x ^ 0x01) * 0x04))
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#define AES_REG_IV(x) (0x20 + ((x) * 0x04))
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#define AES_REG_CTRL 0x30
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#define AES_REG_CTRL_CTR_WIDTH (1 << 7)
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#define AES_REG_CTRL_CTR (1 << 6)
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#define AES_REG_CTRL_CBC (1 << 5)
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#define AES_REG_CTRL_KEY_SIZE (3 << 3)
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#define AES_REG_CTRL_DIRECTION (1 << 2)
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#define AES_REG_CTRL_INPUT_READY (1 << 1)
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#define AES_REG_CTRL_OUTPUT_READY (1 << 0)
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#define AES_REG_DATA 0x34
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#define AES_REG_DATA_N(x) (0x34 + ((x) * 0x04))
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#define AES_REG_REV 0x44
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#define AES_REG_REV_MAJOR 0xF0
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#define AES_REG_REV_MINOR 0x0F
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#define AES_REG_MASK 0x48
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#define AES_REG_MASK_SIDLE (1 << 6)
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#define AES_REG_MASK_START (1 << 5)
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#define AES_REG_MASK_DMA_OUT_EN (1 << 3)
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#define AES_REG_MASK_DMA_IN_EN (1 << 2)
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#define AES_REG_MASK_SOFTRESET (1 << 1)
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#define AES_REG_AUTOIDLE (1 << 0)
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#define AES_REG_SYSSTATUS 0x4C
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#define AES_REG_SYSSTATUS_RESETDONE (1 << 0)
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#define DEFAULT_TIMEOUT (5*HZ)
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#define FLAGS_MODE_MASK 0x000f
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#define FLAGS_ENCRYPT BIT(0)
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#define FLAGS_CBC BIT(1)
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#define FLAGS_GIV BIT(2)
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#define FLAGS_INIT BIT(4)
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#define FLAGS_FAST BIT(5)
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#define FLAGS_BUSY BIT(6)
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struct omap_aes_ctx {
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struct omap_aes_dev *dd;
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int keylen;
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u32 key[AES_KEYSIZE_256 / sizeof(u32)];
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unsigned long flags;
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};
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struct omap_aes_reqctx {
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unsigned long mode;
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};
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#define OMAP_AES_QUEUE_LENGTH 1
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#define OMAP_AES_CACHE_SIZE 0
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struct omap_aes_dev {
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struct list_head list;
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unsigned long phys_base;
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void __iomem *io_base;
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struct clk *iclk;
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struct omap_aes_ctx *ctx;
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struct device *dev;
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unsigned long flags;
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int err;
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spinlock_t lock;
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struct crypto_queue queue;
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struct tasklet_struct done_task;
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struct tasklet_struct queue_task;
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struct ablkcipher_request *req;
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size_t total;
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struct scatterlist *in_sg;
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size_t in_offset;
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struct scatterlist *out_sg;
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size_t out_offset;
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size_t buflen;
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void *buf_in;
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size_t dma_size;
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int dma_in;
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int dma_lch_in;
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dma_addr_t dma_addr_in;
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void *buf_out;
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int dma_out;
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int dma_lch_out;
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dma_addr_t dma_addr_out;
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};
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/* keep registered devices data here */
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static LIST_HEAD(dev_list);
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static DEFINE_SPINLOCK(list_lock);
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static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
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{
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return __raw_readl(dd->io_base + offset);
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}
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static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
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u32 value)
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{
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__raw_writel(value, dd->io_base + offset);
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}
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static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
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u32 value, u32 mask)
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{
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u32 val;
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val = omap_aes_read(dd, offset);
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val &= ~mask;
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val |= value;
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omap_aes_write(dd, offset, val);
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}
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static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
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u32 *value, int count)
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{
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for (; count--; value++, offset += 4)
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omap_aes_write(dd, offset, *value);
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}
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static int omap_aes_wait(struct omap_aes_dev *dd, u32 offset, u32 bit)
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{
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unsigned long timeout = jiffies + DEFAULT_TIMEOUT;
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while (!(omap_aes_read(dd, offset) & bit)) {
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if (time_is_before_jiffies(timeout)) {
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dev_err(dd->dev, "omap-aes timeout\n");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int omap_aes_hw_init(struct omap_aes_dev *dd)
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{
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/*
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* clocks are enabled when request starts and disabled when finished.
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* It may be long delays between requests.
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* Device might go to off mode to save power.
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*/
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clk_enable(dd->iclk);
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if (!(dd->flags & FLAGS_INIT)) {
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/* is it necessary to reset before every operation? */
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omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_SOFTRESET,
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AES_REG_MASK_SOFTRESET);
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/*
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* prevent OCP bus error (SRESP) in case an access to the module
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* is performed while the module is coming out of soft reset
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*/
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__asm__ __volatile__("nop");
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__asm__ __volatile__("nop");
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if (omap_aes_wait(dd, AES_REG_SYSSTATUS,
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AES_REG_SYSSTATUS_RESETDONE))
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return -ETIMEDOUT;
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dd->flags |= FLAGS_INIT;
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dd->err = 0;
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}
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return 0;
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}
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static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
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{
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unsigned int key32;
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int i, err;
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u32 val, mask;
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err = omap_aes_hw_init(dd);
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if (err)
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return err;
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val = 0;
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if (dd->dma_lch_out >= 0)
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val |= AES_REG_MASK_DMA_OUT_EN;
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if (dd->dma_lch_in >= 0)
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val |= AES_REG_MASK_DMA_IN_EN;
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mask = AES_REG_MASK_DMA_IN_EN | AES_REG_MASK_DMA_OUT_EN;
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omap_aes_write_mask(dd, AES_REG_MASK, val, mask);
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key32 = dd->ctx->keylen / sizeof(u32);
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/* it seems a key should always be set even if it has not changed */
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for (i = 0; i < key32; i++) {
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omap_aes_write(dd, AES_REG_KEY(i),
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__le32_to_cpu(dd->ctx->key[i]));
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}
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if ((dd->flags & FLAGS_CBC) && dd->req->info)
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omap_aes_write_n(dd, AES_REG_IV(0), dd->req->info, 4);
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val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
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if (dd->flags & FLAGS_CBC)
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val |= AES_REG_CTRL_CBC;
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if (dd->flags & FLAGS_ENCRYPT)
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val |= AES_REG_CTRL_DIRECTION;
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mask = AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
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AES_REG_CTRL_KEY_SIZE;
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omap_aes_write_mask(dd, AES_REG_CTRL, val, mask);
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/* IN */
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omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
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dd->phys_base + AES_REG_DATA, 0, 4);
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omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
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omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
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/* OUT */
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omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
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dd->phys_base + AES_REG_DATA, 0, 4);
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omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
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omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
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return 0;
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}
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static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
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{
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struct omap_aes_dev *dd = NULL, *tmp;
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spin_lock_bh(&list_lock);
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if (!ctx->dd) {
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list_for_each_entry(tmp, &dev_list, list) {
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/* FIXME: take fist available aes core */
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dd = tmp;
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break;
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}
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ctx->dd = dd;
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} else {
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/* already found before */
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dd = ctx->dd;
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}
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spin_unlock_bh(&list_lock);
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return dd;
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}
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static void omap_aes_dma_callback(int lch, u16 ch_status, void *data)
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{
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struct omap_aes_dev *dd = data;
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if (ch_status != OMAP_DMA_BLOCK_IRQ) {
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pr_err("omap-aes DMA error status: 0x%hx\n", ch_status);
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dd->err = -EIO;
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dd->flags &= ~FLAGS_INIT; /* request to re-initialize */
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} else if (lch == dd->dma_lch_in) {
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return;
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}
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/* dma_lch_out - completed */
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tasklet_schedule(&dd->done_task);
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}
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static int omap_aes_dma_init(struct omap_aes_dev *dd)
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{
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int err = -ENOMEM;
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dd->dma_lch_out = -1;
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dd->dma_lch_in = -1;
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dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
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dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
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dd->buflen = PAGE_SIZE << OMAP_AES_CACHE_SIZE;
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dd->buflen &= ~(AES_BLOCK_SIZE - 1);
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if (!dd->buf_in || !dd->buf_out) {
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dev_err(dd->dev, "unable to alloc pages.\n");
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goto err_alloc;
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}
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/* MAP here */
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dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, dd->buflen,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
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dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
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err = -EINVAL;
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goto err_map_in;
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}
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dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, dd->buflen,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
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dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
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err = -EINVAL;
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goto err_map_out;
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}
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err = omap_request_dma(dd->dma_in, "omap-aes-rx",
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omap_aes_dma_callback, dd, &dd->dma_lch_in);
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if (err) {
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dev_err(dd->dev, "Unable to request DMA channel\n");
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goto err_dma_in;
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}
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err = omap_request_dma(dd->dma_out, "omap-aes-tx",
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omap_aes_dma_callback, dd, &dd->dma_lch_out);
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if (err) {
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dev_err(dd->dev, "Unable to request DMA channel\n");
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goto err_dma_out;
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}
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return 0;
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err_dma_out:
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omap_free_dma(dd->dma_lch_in);
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err_dma_in:
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dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
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DMA_FROM_DEVICE);
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err_map_out:
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dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
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err_map_in:
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free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
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free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
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err_alloc:
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if (err)
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pr_err("error: %d\n", err);
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return err;
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}
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static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
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{
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omap_free_dma(dd->dma_lch_out);
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omap_free_dma(dd->dma_lch_in);
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dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
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DMA_FROM_DEVICE);
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dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
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free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
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free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
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}
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static void sg_copy_buf(void *buf, struct scatterlist *sg,
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unsigned int start, unsigned int nbytes, int out)
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{
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struct scatter_walk walk;
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if (!nbytes)
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return;
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scatterwalk_start(&walk, sg);
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scatterwalk_advance(&walk, start);
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scatterwalk_copychunks(buf, &walk, nbytes, out);
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scatterwalk_done(&walk, out, 0);
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}
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static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf,
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size_t buflen, size_t total, int out)
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{
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unsigned int count, off = 0;
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while (buflen && total) {
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count = min((*sg)->length - *offset, total);
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count = min(count, buflen);
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if (!count)
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return off;
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/*
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* buflen and total are AES_BLOCK_SIZE size aligned,
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* so count should be also aligned
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*/
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sg_copy_buf(buf + off, *sg, *offset, count, out);
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off += count;
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buflen -= count;
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*offset += count;
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total -= count;
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if (*offset == (*sg)->length) {
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*sg = sg_next(*sg);
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if (*sg)
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*offset = 0;
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else
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total = 0;
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}
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}
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return off;
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}
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static int omap_aes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in,
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dma_addr_t dma_addr_out, int length)
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{
|
|
struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct omap_aes_dev *dd = ctx->dd;
|
|
int len32;
|
|
|
|
pr_debug("len: %d\n", length);
|
|
|
|
dd->dma_size = length;
|
|
|
|
if (!(dd->flags & FLAGS_FAST))
|
|
dma_sync_single_for_device(dd->dev, dma_addr_in, length,
|
|
DMA_TO_DEVICE);
|
|
|
|
len32 = DIV_ROUND_UP(length, sizeof(u32));
|
|
|
|
/* IN */
|
|
omap_set_dma_transfer_params(dd->dma_lch_in, OMAP_DMA_DATA_TYPE_S32,
|
|
len32, 1, OMAP_DMA_SYNC_PACKET, dd->dma_in,
|
|
OMAP_DMA_DST_SYNC);
|
|
|
|
omap_set_dma_src_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_POST_INC,
|
|
dma_addr_in, 0, 0);
|
|
|
|
/* OUT */
|
|
omap_set_dma_transfer_params(dd->dma_lch_out, OMAP_DMA_DATA_TYPE_S32,
|
|
len32, 1, OMAP_DMA_SYNC_PACKET,
|
|
dd->dma_out, OMAP_DMA_SRC_SYNC);
|
|
|
|
omap_set_dma_dest_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_POST_INC,
|
|
dma_addr_out, 0, 0);
|
|
|
|
omap_start_dma(dd->dma_lch_in);
|
|
omap_start_dma(dd->dma_lch_out);
|
|
|
|
/* start DMA or disable idle mode */
|
|
omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START,
|
|
AES_REG_MASK_START);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
|
|
{
|
|
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
|
|
crypto_ablkcipher_reqtfm(dd->req));
|
|
int err, fast = 0, in, out;
|
|
size_t count;
|
|
dma_addr_t addr_in, addr_out;
|
|
|
|
pr_debug("total: %d\n", dd->total);
|
|
|
|
if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) {
|
|
/* check for alignment */
|
|
in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32));
|
|
out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32));
|
|
|
|
fast = in && out;
|
|
}
|
|
|
|
if (fast) {
|
|
count = min(dd->total, sg_dma_len(dd->in_sg));
|
|
count = min(count, sg_dma_len(dd->out_sg));
|
|
|
|
if (count != dd->total) {
|
|
pr_err("request length != buffer length\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pr_debug("fast\n");
|
|
|
|
err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
if (!err) {
|
|
dev_err(dd->dev, "dma_map_sg() error\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = dma_map_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
|
|
if (!err) {
|
|
dev_err(dd->dev, "dma_map_sg() error\n");
|
|
dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
return -EINVAL;
|
|
}
|
|
|
|
addr_in = sg_dma_address(dd->in_sg);
|
|
addr_out = sg_dma_address(dd->out_sg);
|
|
|
|
dd->flags |= FLAGS_FAST;
|
|
|
|
} else {
|
|
/* use cache buffers */
|
|
count = sg_copy(&dd->in_sg, &dd->in_offset, dd->buf_in,
|
|
dd->buflen, dd->total, 0);
|
|
|
|
addr_in = dd->dma_addr_in;
|
|
addr_out = dd->dma_addr_out;
|
|
|
|
dd->flags &= ~FLAGS_FAST;
|
|
|
|
}
|
|
|
|
dd->total -= count;
|
|
|
|
err = omap_aes_crypt_dma(tfm, addr_in, addr_out, count);
|
|
if (err) {
|
|
dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
|
|
{
|
|
struct ablkcipher_request *req = dd->req;
|
|
|
|
pr_debug("err: %d\n", err);
|
|
|
|
clk_disable(dd->iclk);
|
|
dd->flags &= ~FLAGS_BUSY;
|
|
|
|
req->base.complete(&req->base, err);
|
|
}
|
|
|
|
static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
|
|
{
|
|
int err = 0;
|
|
size_t count;
|
|
|
|
pr_debug("total: %d\n", dd->total);
|
|
|
|
omap_aes_write_mask(dd, AES_REG_MASK, 0, AES_REG_MASK_START);
|
|
|
|
omap_stop_dma(dd->dma_lch_in);
|
|
omap_stop_dma(dd->dma_lch_out);
|
|
|
|
if (dd->flags & FLAGS_FAST) {
|
|
dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
|
|
dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
} else {
|
|
dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
|
|
dd->dma_size, DMA_FROM_DEVICE);
|
|
|
|
/* copy data */
|
|
count = sg_copy(&dd->out_sg, &dd->out_offset, dd->buf_out,
|
|
dd->buflen, dd->dma_size, 1);
|
|
if (count != dd->dma_size) {
|
|
err = -EINVAL;
|
|
pr_err("not all data converted: %u\n", count);
|
|
}
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int omap_aes_handle_queue(struct omap_aes_dev *dd,
|
|
struct ablkcipher_request *req)
|
|
{
|
|
struct crypto_async_request *async_req, *backlog;
|
|
struct omap_aes_ctx *ctx;
|
|
struct omap_aes_reqctx *rctx;
|
|
unsigned long flags;
|
|
int err, ret = 0;
|
|
|
|
spin_lock_irqsave(&dd->lock, flags);
|
|
if (req)
|
|
ret = ablkcipher_enqueue_request(&dd->queue, req);
|
|
if (dd->flags & FLAGS_BUSY) {
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
return ret;
|
|
}
|
|
backlog = crypto_get_backlog(&dd->queue);
|
|
async_req = crypto_dequeue_request(&dd->queue);
|
|
if (async_req)
|
|
dd->flags |= FLAGS_BUSY;
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
if (!async_req)
|
|
return ret;
|
|
|
|
if (backlog)
|
|
backlog->complete(backlog, -EINPROGRESS);
|
|
|
|
req = ablkcipher_request_cast(async_req);
|
|
|
|
/* assign new request to device */
|
|
dd->req = req;
|
|
dd->total = req->nbytes;
|
|
dd->in_offset = 0;
|
|
dd->in_sg = req->src;
|
|
dd->out_offset = 0;
|
|
dd->out_sg = req->dst;
|
|
|
|
rctx = ablkcipher_request_ctx(req);
|
|
ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
|
|
rctx->mode &= FLAGS_MODE_MASK;
|
|
dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
|
|
|
|
dd->ctx = ctx;
|
|
ctx->dd = dd;
|
|
|
|
err = omap_aes_write_ctrl(dd);
|
|
if (!err)
|
|
err = omap_aes_crypt_dma_start(dd);
|
|
if (err) {
|
|
/* aes_task will not finish it, so do it here */
|
|
omap_aes_finish_req(dd, err);
|
|
tasklet_schedule(&dd->queue_task);
|
|
}
|
|
|
|
return ret; /* return ret, which is enqueue return value */
|
|
}
|
|
|
|
static void omap_aes_done_task(unsigned long data)
|
|
{
|
|
struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
|
|
int err;
|
|
|
|
pr_debug("enter\n");
|
|
|
|
err = omap_aes_crypt_dma_stop(dd);
|
|
|
|
err = dd->err ? : err;
|
|
|
|
if (dd->total && !err) {
|
|
err = omap_aes_crypt_dma_start(dd);
|
|
if (!err)
|
|
return; /* DMA started. Not fininishing. */
|
|
}
|
|
|
|
omap_aes_finish_req(dd, err);
|
|
omap_aes_handle_queue(dd, NULL);
|
|
|
|
pr_debug("exit\n");
|
|
}
|
|
|
|
static void omap_aes_queue_task(unsigned long data)
|
|
{
|
|
struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
|
|
|
|
omap_aes_handle_queue(dd, NULL);
|
|
}
|
|
|
|
static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
|
|
{
|
|
struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
|
|
crypto_ablkcipher_reqtfm(req));
|
|
struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
|
|
struct omap_aes_dev *dd;
|
|
|
|
pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
|
|
!!(mode & FLAGS_ENCRYPT),
|
|
!!(mode & FLAGS_CBC));
|
|
|
|
if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
|
|
pr_err("request size is not exact amount of AES blocks\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dd = omap_aes_find_dev(ctx);
|
|
if (!dd)
|
|
return -ENODEV;
|
|
|
|
rctx->mode = mode;
|
|
|
|
return omap_aes_handle_queue(dd, req);
|
|
}
|
|
|
|
/* ********************** ALG API ************************************ */
|
|
|
|
static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
|
|
unsigned int keylen)
|
|
{
|
|
struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
|
|
|
|
if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
|
|
keylen != AES_KEYSIZE_256)
|
|
return -EINVAL;
|
|
|
|
pr_debug("enter, keylen: %d\n", keylen);
|
|
|
|
memcpy(ctx->key, key, keylen);
|
|
ctx->keylen = keylen;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, 0);
|
|
}
|
|
|
|
static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
|
|
}
|
|
|
|
static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_CBC);
|
|
}
|
|
|
|
static int omap_aes_cra_init(struct crypto_tfm *tfm)
|
|
{
|
|
pr_debug("enter\n");
|
|
|
|
tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_aes_cra_exit(struct crypto_tfm *tfm)
|
|
{
|
|
pr_debug("enter\n");
|
|
}
|
|
|
|
/* ********************** ALGS ************************************ */
|
|
|
|
static struct crypto_alg algs[] = {
|
|
{
|
|
.cra_name = "ecb(aes)",
|
|
.cra_driver_name = "ecb-aes-omap",
|
|
.cra_priority = 100,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
CRYPTO_ALG_ASYNC,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_aes_cra_init,
|
|
.cra_exit = omap_aes_cra_exit,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.setkey = omap_aes_setkey,
|
|
.encrypt = omap_aes_ecb_encrypt,
|
|
.decrypt = omap_aes_ecb_decrypt,
|
|
}
|
|
},
|
|
{
|
|
.cra_name = "cbc(aes)",
|
|
.cra_driver_name = "cbc-aes-omap",
|
|
.cra_priority = 100,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
CRYPTO_ALG_ASYNC,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_aes_cra_init,
|
|
.cra_exit = omap_aes_cra_exit,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.setkey = omap_aes_setkey,
|
|
.encrypt = omap_aes_cbc_encrypt,
|
|
.decrypt = omap_aes_cbc_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
static int omap_aes_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct omap_aes_dev *dd;
|
|
struct resource *res;
|
|
int err = -ENOMEM, i, j;
|
|
u32 reg;
|
|
|
|
dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL);
|
|
if (dd == NULL) {
|
|
dev_err(dev, "unable to alloc data struct.\n");
|
|
goto err_data;
|
|
}
|
|
dd->dev = dev;
|
|
platform_set_drvdata(pdev, dd);
|
|
|
|
spin_lock_init(&dd->lock);
|
|
crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
|
|
|
|
/* Get the base address */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(dev, "invalid resource type\n");
|
|
err = -ENODEV;
|
|
goto err_res;
|
|
}
|
|
dd->phys_base = res->start;
|
|
|
|
/* Get the DMA */
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
if (!res)
|
|
dev_info(dev, "no DMA info\n");
|
|
else
|
|
dd->dma_out = res->start;
|
|
|
|
/* Get the DMA */
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
|
if (!res)
|
|
dev_info(dev, "no DMA info\n");
|
|
else
|
|
dd->dma_in = res->start;
|
|
|
|
/* Initializing the clock */
|
|
dd->iclk = clk_get(dev, "ick");
|
|
if (IS_ERR(dd->iclk)) {
|
|
dev_err(dev, "clock intialization failed.\n");
|
|
err = PTR_ERR(dd->iclk);
|
|
goto err_res;
|
|
}
|
|
|
|
dd->io_base = ioremap(dd->phys_base, SZ_4K);
|
|
if (!dd->io_base) {
|
|
dev_err(dev, "can't ioremap\n");
|
|
err = -ENOMEM;
|
|
goto err_io;
|
|
}
|
|
|
|
clk_enable(dd->iclk);
|
|
reg = omap_aes_read(dd, AES_REG_REV);
|
|
dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
|
|
(reg & AES_REG_REV_MAJOR) >> 4, reg & AES_REG_REV_MINOR);
|
|
clk_disable(dd->iclk);
|
|
|
|
tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
|
|
tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
|
|
|
|
err = omap_aes_dma_init(dd);
|
|
if (err)
|
|
goto err_dma;
|
|
|
|
INIT_LIST_HEAD(&dd->list);
|
|
spin_lock(&list_lock);
|
|
list_add_tail(&dd->list, &dev_list);
|
|
spin_unlock(&list_lock);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(algs); i++) {
|
|
pr_debug("i: %d\n", i);
|
|
err = crypto_register_alg(&algs[i]);
|
|
if (err)
|
|
goto err_algs;
|
|
}
|
|
|
|
pr_info("probe() done\n");
|
|
|
|
return 0;
|
|
err_algs:
|
|
for (j = 0; j < i; j++)
|
|
crypto_unregister_alg(&algs[j]);
|
|
omap_aes_dma_cleanup(dd);
|
|
err_dma:
|
|
tasklet_kill(&dd->done_task);
|
|
tasklet_kill(&dd->queue_task);
|
|
iounmap(dd->io_base);
|
|
err_io:
|
|
clk_put(dd->iclk);
|
|
err_res:
|
|
kfree(dd);
|
|
dd = NULL;
|
|
err_data:
|
|
dev_err(dev, "initialization failed.\n");
|
|
return err;
|
|
}
|
|
|
|
static int omap_aes_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_aes_dev *dd = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
if (!dd)
|
|
return -ENODEV;
|
|
|
|
spin_lock(&list_lock);
|
|
list_del(&dd->list);
|
|
spin_unlock(&list_lock);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(algs); i++)
|
|
crypto_unregister_alg(&algs[i]);
|
|
|
|
tasklet_kill(&dd->done_task);
|
|
tasklet_kill(&dd->queue_task);
|
|
omap_aes_dma_cleanup(dd);
|
|
iounmap(dd->io_base);
|
|
clk_put(dd->iclk);
|
|
kfree(dd);
|
|
dd = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver omap_aes_driver = {
|
|
.probe = omap_aes_probe,
|
|
.remove = omap_aes_remove,
|
|
.driver = {
|
|
.name = "omap-aes",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init omap_aes_mod_init(void)
|
|
{
|
|
pr_info("loading %s driver\n", "omap-aes");
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return platform_driver_register(&omap_aes_driver);
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}
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|
|
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static void __exit omap_aes_mod_exit(void)
|
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{
|
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platform_driver_unregister(&omap_aes_driver);
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}
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module_init(omap_aes_mod_init);
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module_exit(omap_aes_mod_exit);
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|
|
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MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
|
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Dmitry Kasatkin");
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