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619053220a
Current komeda driver uses three dedicated clks for a specific purpose: - mclk: main engine clock - pclk: APB clock - pipeline->aclk: AXI clock. But per spec the komeda HW only has three input clks: - ACLK: used for AXI masters, APB slave and most pipeline processing - PXCLK for pipeline 0: output pixel clock for pipeline 0 - PXCLK for pipeline 1: output pixel clock for pipeline 1 So one ACLK is enough, no need to split it to three mclk/pclk/axiclk. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
78 lines
2.2 KiB
Text
78 lines
2.2 KiB
Text
Device Tree bindings for Arm Komeda display driver
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Required properties:
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- compatible: Should be "arm,mali-d71"
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- reg: Physical base address and length of the registers in the system
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- interrupts: the interrupt line number of the device in the system
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- clocks: A list of phandle + clock-specifier pairs, one for each entry
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in 'clock-names'
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- clock-names: A list of clock names. It should contain:
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- "aclk": for the main processor clock
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- #address-cells: Must be 1
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- #size-cells: Must be 0
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- iommus: configure the stream id to IOMMU, Must be configured if want to
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enable iommu in display. for how to configure this node please reference
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devicetree/bindings/iommu/arm,smmu-v3.txt,
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devicetree/bindings/iommu/iommu.txt
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Required properties for sub-node: pipeline@nq
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Each device contains one or two pipeline sub-nodes (at least one), each
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pipeline node should provide properties:
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- reg: Zero-indexed identifier for the pipeline
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- clocks: A list of phandle + clock-specifier pairs, one for each entry
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in 'clock-names'
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- clock-names: should contain:
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- "pxclk": pixel clock
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- port: each pipeline connect to an encoder input port. The connection is
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modeled using the OF graph bindings specified in
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Documentation/devicetree/bindings/graph.txt
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Optional properties:
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- memory-region: phandle to a node describing memory (see
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
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to be used for the framebuffer; if not present, the framebuffer may
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be located anywhere in memory.
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Example:
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/ {
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...
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dp0: display@c00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,mali-d71";
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reg = <0xc00000 0x20000>;
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interrupts = <0 168 4>;
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clocks = <&dpu_aclk>;
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clock-names = "aclk";
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iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
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<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
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<&smmu 8>, <&smmu 9>;
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dp0_pipe0: pipeline@0 {
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clocks = <&fpgaosc2>;
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clock-names = "pxclk";
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reg = <0>;
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port {
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dp0_pipe0_out: endpoint {
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remote-endpoint = <&db_dvi0_in>;
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};
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};
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};
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dp0_pipe1: pipeline@1 {
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clocks = <&fpgaosc2>;
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clock-names = "pxclk";
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reg = <1>;
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port {
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dp0_pipe1_out: endpoint {
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remote-endpoint = <&db_dvi1_in>;
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};
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};
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};
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};
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...
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};
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