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b166be0044
On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updating accordingly. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
38 lines
1.2 KiB
Text
38 lines
1.2 KiB
Text
OMAP SoC and Inside-Secure HWRNG Module
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Required properties:
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- compatible : Should contain entries for this and backward compatible
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RNG versions:
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- "ti,omap2-rng" for OMAP2.
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- "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX.
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- "inside-secure,safexcel-eip76" for SoCs with EIP76 IP block
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Note that these two versions are incompatible.
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- ti,hwmods: Name of the hwmod associated with the RNG module
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- reg : Offset and length of the register set for the module
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- interrupts : the interrupt number for the RNG module.
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Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76"
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- clocks: the trng clock source. Only mandatory for the
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"inside-secure,safexcel-eip76" compatible, the second clock is
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needed for the Armada 7K/8K SoCs
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- clock-names: mandatory if there is a second clock, in this case the
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name must be "core" for the first clock and "reg" for the second
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one
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Example:
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/* AM335x */
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rng: rng@48310000 {
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compatible = "ti,omap4-rng";
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ti,hwmods = "rng";
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reg = <0x48310000 0x2000>;
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interrupts = <111>;
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};
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/* SafeXcel IP-76 */
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trng: rng@f2760000 {
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compatible = "inside-secure,safexcel-eip76";
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reg = <0xf2760000 0x7d>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_syscon0 1 25>;
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};
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