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e90ddd813d
Currently the iop3xx platform support code assumes that RedBoot is the bootloader and has already initialized the ATU. Linux should handle this initialization for three reasons: 1/ The memory map that RedBoot sets up is not optimal (page_to_dma and virt_to_phys return different addresses). The effect of this is that using the dma mapping API for the internal bus dma units generates pci bus addresses that are incorrect for the internal bus. 2/ Not all iop platforms use RedBoot 3/ If the ATU is already initialized it indicates that the iop is an add-in card in another host, it does not own the PCI bus, and should not be re-initialized. Changelog: * rather than change nr_controllers to zero, simply do not call pci_common_init Cc: Lennert Buytenhek <kernel@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
195 lines
4.4 KiB
C
195 lines
4.4 KiB
C
/*
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* arch/arm/mach-iop32x/iq80321.c
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*
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* Board support code for the Intel IQ80321 platform.
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_device.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/pci.h>
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#include <asm/mach/time.h>
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#include <asm/mach-types.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/arch/time.h>
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/*
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* IQ80321 timer tick configuration.
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*/
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static void __init iq80321_timer_init(void)
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{
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/* 33.333 MHz crystal. */
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iop_init_time(200000000);
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}
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static struct sys_timer iq80321_timer = {
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.init = iq80321_timer_init,
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.offset = iop_gettimeoffset,
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};
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/*
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* IQ80321 I/O.
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*/
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static struct map_desc iq80321_io_desc[] __initdata = {
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{ /* on-board devices */
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.virtual = IQ80321_UART,
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.pfn = __phys_to_pfn(IQ80321_UART),
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.length = 0x00100000,
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.type = MT_DEVICE,
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},
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};
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void __init iq80321_map_io(void)
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{
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iop3xx_map_io();
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iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
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}
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/*
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* IQ80321 PCI.
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*/
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static inline int __init
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iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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if ((slot == 2 || slot == 6) && pin == 1) {
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/* PCI-X Slot INTA */
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irq = IRQ_IOP32X_XINT2;
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} else if ((slot == 2 || slot == 6) && pin == 2) {
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/* PCI-X Slot INTA */
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irq = IRQ_IOP32X_XINT3;
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} else if ((slot == 2 || slot == 6) && pin == 3) {
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/* PCI-X Slot INTA */
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irq = IRQ_IOP32X_XINT0;
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} else if ((slot == 2 || slot == 6) && pin == 4) {
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/* PCI-X Slot INTA */
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irq = IRQ_IOP32X_XINT1;
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} else if (slot == 4 || slot == 8) {
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/* Gig-E */
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irq = IRQ_IOP32X_XINT0;
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} else {
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printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
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"device PCI:%d:%d:%d\n", dev->bus->number,
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PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
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irq = -1;
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}
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return irq;
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}
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static struct hw_pci iq80321_pci __initdata = {
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.swizzle = pci_std_swizzle,
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.nr_controllers = 1,
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.setup = iop3xx_pci_setup,
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.preinit = iop3xx_pci_preinit,
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.scan = iop3xx_pci_scan_bus,
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.map_irq = iq80321_pci_map_irq,
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};
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static int __init iq80321_pci_init(void)
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{
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if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
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machine_is_iq80321())
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pci_common_init(&iq80321_pci);
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return 0;
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}
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subsys_initcall(iq80321_pci_init);
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/*
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* IQ80321 machine initialisation.
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*/
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static struct physmap_flash_data iq80321_flash_data = {
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.width = 1,
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};
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static struct resource iq80321_flash_resource = {
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.start = 0xf0000000,
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.end = 0xf07fffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device iq80321_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &iq80321_flash_data,
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},
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.num_resources = 1,
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.resource = &iq80321_flash_resource,
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};
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static struct plat_serial8250_port iq80321_serial_port[] = {
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{
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.mapbase = IQ80321_UART,
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.membase = (char *)IQ80321_UART,
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.irq = IRQ_IOP32X_XINT1,
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.flags = UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 0,
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.uartclk = 1843200,
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},
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{ },
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};
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static struct resource iq80321_uart_resource = {
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.start = IQ80321_UART,
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.end = IQ80321_UART + 7,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device iq80321_serial_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = iq80321_serial_port,
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},
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.num_resources = 1,
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.resource = &iq80321_uart_resource,
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};
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static void __init iq80321_init_machine(void)
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{
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platform_device_register(&iop3xx_i2c0_device);
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platform_device_register(&iop3xx_i2c1_device);
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platform_device_register(&iq80321_flash_device);
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platform_device_register(&iq80321_serial_device);
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}
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MACHINE_START(IQ80321, "Intel IQ80321")
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/* Maintainer: Intel Corp. */
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.phys_io = IQ80321_UART,
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.io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
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.boot_params = 0xa0000100,
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.map_io = iq80321_map_io,
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.init_irq = iop32x_init_irq,
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.timer = &iq80321_timer,
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.init_machine = iq80321_init_machine,
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MACHINE_END
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