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088e88be5a
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. The IP block contains settings for the PHY and a PLL. The PLL mode is configurable through a dedicated #phy-cell in .dts. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
11 lines
373 B
C
11 lines
373 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#define LANTIQ_PCIE_PHY_MODE_25MHZ 0
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#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1
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#define LANTIQ_PCIE_PHY_MODE_36MHZ 2
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#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3
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#define LANTIQ_PCIE_PHY_MODE_100MHZ 4
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#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5
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