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BCM6368 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
16 lines
412 B
C
16 lines
412 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __DT_BINDINGS_RESET_BCM6368_H
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#define __DT_BINDINGS_RESET_BCM6368_H
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#define BCM6368_RST_SPI 0
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#define BCM6368_RST_MPI 3
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#define BCM6368_RST_IPSEC 4
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#define BCM6368_RST_EPHY 6
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#define BCM6368_RST_SAR 7
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#define BCM6368_RST_SWITCH 10
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#define BCM6368_RST_USBD 11
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#define BCM6368_RST_USBH 12
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#define BCM6368_RST_PCM 13
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#endif /* __DT_BINDINGS_RESET_BCM6368_H */
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