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0482a4e6de
While no information about the H6 RSB controller is included in the datasheet or manual, the vendor BSP and power management blob both reference the RSB clock parent and register address. These values were verified by experimentation. Since this clock/reset are added late, the specifier is added at the end to maintain the existing DT binding. The code is kept in register order. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
18 lines
459 B
C
18 lines
459 B
C
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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*/
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#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
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#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
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#define RST_R_APB1_TIMER 0
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#define RST_R_APB1_TWD 1
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#define RST_R_APB1_PWM 2
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#define RST_R_APB2_UART 3
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#define RST_R_APB2_I2C 4
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#define RST_R_APB1_IR 5
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#define RST_R_APB1_W1 6
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#define RST_R_APB2_RSB 7
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#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
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