mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
![Andre Przywara](/assets/img/avatar_default.png)
While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
|
/*
|
|
* Copyright (C) 2020 Arm Ltd.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_
|
|
#define _DT_BINDINGS_RESET_SUN50I_H616_H_
|
|
|
|
#define RST_MBUS 0
|
|
#define RST_BUS_DE 1
|
|
#define RST_BUS_DEINTERLACE 2
|
|
#define RST_BUS_GPU 3
|
|
#define RST_BUS_CE 4
|
|
#define RST_BUS_VE 5
|
|
#define RST_BUS_DMA 6
|
|
#define RST_BUS_HSTIMER 7
|
|
#define RST_BUS_DBG 8
|
|
#define RST_BUS_PSI 9
|
|
#define RST_BUS_PWM 10
|
|
#define RST_BUS_IOMMU 11
|
|
#define RST_BUS_DRAM 12
|
|
#define RST_BUS_NAND 13
|
|
#define RST_BUS_MMC0 14
|
|
#define RST_BUS_MMC1 15
|
|
#define RST_BUS_MMC2 16
|
|
#define RST_BUS_UART0 17
|
|
#define RST_BUS_UART1 18
|
|
#define RST_BUS_UART2 19
|
|
#define RST_BUS_UART3 20
|
|
#define RST_BUS_UART4 21
|
|
#define RST_BUS_UART5 22
|
|
#define RST_BUS_I2C0 23
|
|
#define RST_BUS_I2C1 24
|
|
#define RST_BUS_I2C2 25
|
|
#define RST_BUS_I2C3 26
|
|
#define RST_BUS_I2C4 27
|
|
#define RST_BUS_SPI0 28
|
|
#define RST_BUS_SPI1 29
|
|
#define RST_BUS_EMAC0 30
|
|
#define RST_BUS_EMAC1 31
|
|
#define RST_BUS_TS 32
|
|
#define RST_BUS_THS 33
|
|
#define RST_BUS_SPDIF 34
|
|
#define RST_BUS_DMIC 35
|
|
#define RST_BUS_AUDIO_CODEC 36
|
|
#define RST_BUS_AUDIO_HUB 37
|
|
#define RST_USB_PHY0 38
|
|
#define RST_USB_PHY1 39
|
|
#define RST_USB_PHY2 40
|
|
#define RST_USB_PHY3 41
|
|
#define RST_BUS_OHCI0 42
|
|
#define RST_BUS_OHCI1 43
|
|
#define RST_BUS_OHCI2 44
|
|
#define RST_BUS_OHCI3 45
|
|
#define RST_BUS_EHCI0 46
|
|
#define RST_BUS_EHCI1 47
|
|
#define RST_BUS_EHCI2 48
|
|
#define RST_BUS_EHCI3 49
|
|
#define RST_BUS_OTG 50
|
|
#define RST_BUS_HDMI 51
|
|
#define RST_BUS_HDMI_SUB 52
|
|
#define RST_BUS_TCON_TOP 53
|
|
#define RST_BUS_TCON_TV0 54
|
|
#define RST_BUS_TCON_TV1 55
|
|
#define RST_BUS_TVE_TOP 56
|
|
#define RST_BUS_TVE0 57
|
|
#define RST_BUS_HDCP 58
|
|
#define RST_BUS_KEYADC 59
|
|
|
|
#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
|