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9e2b3e834c
Commit b24413180f ("License cleanup: add SPDX GPL-2.0 license
identifier to files with no license") was meant to do a tree-wide
cleanup for files without any license information by adding a SPDX
GPL-2.0 line to them.
Unfortunately this was applied even to several Xen-related headers
which have been originally under the MIT license, but obviously have
been copied to the Linux tree from the Xen project without keeping the
license boiler plate as required.
Correct that by changing the license of those files back to "MIT".
Some files still contain the MIT license text. Replace that by the
related SPDX line.
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Link: https://lore.kernel.org/r/20211015143312.29900-1-jgross@suse.com
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
116 lines
2.8 KiB
C
116 lines
2.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (c) 2015, Roger Pau Monne <roger.pau@citrix.com>
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*/
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#ifndef __XEN_PUBLIC_HVM_HVM_VCPU_H__
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#define __XEN_PUBLIC_HVM_HVM_VCPU_H__
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#include "../xen.h"
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struct vcpu_hvm_x86_32 {
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uint32_t eax;
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uint32_t ecx;
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uint32_t edx;
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uint32_t ebx;
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uint32_t esp;
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uint32_t ebp;
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uint32_t esi;
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uint32_t edi;
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uint32_t eip;
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uint32_t eflags;
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uint32_t cr0;
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uint32_t cr3;
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uint32_t cr4;
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uint32_t pad1;
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/*
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* EFER should only be used to set the NXE bit (if required)
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* when starting a vCPU in 32bit mode with paging enabled or
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* to set the LME/LMA bits in order to start the vCPU in
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* compatibility mode.
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*/
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uint64_t efer;
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uint32_t cs_base;
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uint32_t ds_base;
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uint32_t ss_base;
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uint32_t es_base;
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uint32_t tr_base;
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uint32_t cs_limit;
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uint32_t ds_limit;
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uint32_t ss_limit;
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uint32_t es_limit;
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uint32_t tr_limit;
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uint16_t cs_ar;
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uint16_t ds_ar;
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uint16_t ss_ar;
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uint16_t es_ar;
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uint16_t tr_ar;
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uint16_t pad2[3];
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};
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/*
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* The layout of the _ar fields of the segment registers is the
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* following:
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*
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* Bits [0,3]: type (bits 40-43).
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* Bit 4: s (descriptor type, bit 44).
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* Bit [5,6]: dpl (descriptor privilege level, bits 45-46).
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* Bit 7: p (segment-present, bit 47).
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* Bit 8: avl (available for system software, bit 52).
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* Bit 9: l (64-bit code segment, bit 53).
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* Bit 10: db (meaning depends on the segment, bit 54).
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* Bit 11: g (granularity, bit 55)
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* Bits [12,15]: unused, must be blank.
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*
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* A more complete description of the meaning of this fields can be
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* obtained from the Intel SDM, Volume 3, section 3.4.5.
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*/
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struct vcpu_hvm_x86_64 {
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uint64_t rax;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rbx;
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uint64_t rsp;
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uint64_t rbp;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t rip;
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uint64_t rflags;
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uint64_t cr0;
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uint64_t cr3;
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uint64_t cr4;
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uint64_t efer;
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/*
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* Using VCPU_HVM_MODE_64B implies that the vCPU is launched
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* directly in long mode, so the cached parts of the segment
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* registers get set to match that environment.
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*
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* If the user wants to launch the vCPU in compatibility mode
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* the 32-bit structure should be used instead.
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*/
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};
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struct vcpu_hvm_context {
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#define VCPU_HVM_MODE_32B 0 /* 32bit fields of the structure will be used. */
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#define VCPU_HVM_MODE_64B 1 /* 64bit fields of the structure will be used. */
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uint32_t mode;
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uint32_t pad;
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/* CPU registers. */
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union {
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struct vcpu_hvm_x86_32 x86_32;
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struct vcpu_hvm_x86_64 x86_64;
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} cpu_regs;
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};
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typedef struct vcpu_hvm_context vcpu_hvm_context_t;
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#endif /* __XEN_PUBLIC_HVM_HVM_VCPU_H__ */
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