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![David Woodhouse](/assets/img/avatar_default.png)
Dan Carpenter pointed out an error path which could lead to us
dereferencing the 'svm' pointer after we know it to be NULL because the
PASID lookup failed. Fix that, and make it less likely to happen again.
Fixes: a222a7f0bb
('iommu/vt-d: Implement page request handling')
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
587 lines
15 KiB
C
587 lines
15 KiB
C
/*
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* Copyright © 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* Authors: David Woodhouse <dwmw2@infradead.org>
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*/
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#include <linux/intel-iommu.h>
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#include <linux/mmu_notifier.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/intel-svm.h>
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#include <linux/rculist.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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#include <linux/dmar.h>
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#include <linux/interrupt.h>
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static irqreturn_t prq_event_thread(int irq, void *d);
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struct pasid_entry {
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u64 val;
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};
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struct pasid_state_entry {
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u64 val;
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};
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int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
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{
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struct page *pages;
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int order;
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order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT;
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if (order < 0)
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order = 0;
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
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if (!pages) {
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pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
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iommu->name);
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return -ENOMEM;
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}
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iommu->pasid_table = page_address(pages);
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pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
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if (ecap_dis(iommu->ecap)) {
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
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if (pages)
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iommu->pasid_state_table = page_address(pages);
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else
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pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
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iommu->name);
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}
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idr_init(&iommu->pasid_idr);
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return 0;
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}
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int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
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{
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int order;
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order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT;
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if (order < 0)
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order = 0;
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if (iommu->pasid_table) {
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free_pages((unsigned long)iommu->pasid_table, order);
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iommu->pasid_table = NULL;
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}
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if (iommu->pasid_state_table) {
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free_pages((unsigned long)iommu->pasid_state_table, order);
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iommu->pasid_state_table = NULL;
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}
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idr_destroy(&iommu->pasid_idr);
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return 0;
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}
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#define PRQ_ORDER 0
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int intel_svm_enable_prq(struct intel_iommu *iommu)
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{
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struct page *pages;
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int irq, ret;
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
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if (!pages) {
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pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
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iommu->name);
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return -ENOMEM;
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}
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iommu->prq = page_address(pages);
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irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
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if (irq <= 0) {
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pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
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iommu->name);
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ret = -EINVAL;
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err:
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return ret;
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}
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iommu->pr_irq = irq;
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snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
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ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
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iommu->prq_name, iommu);
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if (ret) {
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pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
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iommu->name);
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dmar_free_hwirq(irq);
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goto err;
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}
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
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return 0;
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}
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int intel_svm_finish_prq(struct intel_iommu *iommu)
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{
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
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free_irq(iommu->pr_irq, iommu);
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dmar_free_hwirq(iommu->pr_irq);
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iommu->pr_irq = 0;
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return 0;
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}
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static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
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unsigned long address, int pages, int ih)
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{
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struct qi_desc desc;
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int mask = ilog2(__roundup_pow_of_two(pages));
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if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap) ||
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mask > cap_max_amask_val(svm->iommu->cap)) {
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desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
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QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
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desc.high = 0;
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} else {
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desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
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QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
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desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(1) |
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QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
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}
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qi_submit_sync(&desc, svm->iommu);
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if (sdev->dev_iotlb) {
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desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
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QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
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if (mask) {
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unsigned long adr, delta;
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/* Least significant zero bits in the address indicate the
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* range of the request. So mask them out according to the
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* size. */
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adr = address & ((1<<(VTD_PAGE_SHIFT + mask)) - 1);
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/* Now ensure that we round down further if the original
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* request was not aligned w.r.t. its size */
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delta = address - adr;
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if (delta + (pages << VTD_PAGE_SHIFT) >= (1 << (VTD_PAGE_SHIFT + mask)))
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adr &= ~(1 << (VTD_PAGE_SHIFT + mask));
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desc.high = QI_DEV_EIOTLB_ADDR(adr) | QI_DEV_EIOTLB_SIZE;
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} else {
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desc.high = QI_DEV_EIOTLB_ADDR(address);
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}
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qi_submit_sync(&desc, svm->iommu);
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}
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}
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static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
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int pages, int ih)
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{
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struct intel_svm_dev *sdev;
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/* Try deferred invalidate if available */
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if (svm->iommu->pasid_state_table &&
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!cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
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return;
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rcu_read_lock();
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list_for_each_entry_rcu(sdev, &svm->devs, list)
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intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
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rcu_read_unlock();
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}
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static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
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unsigned long address, pte_t pte)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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intel_flush_svm_range(svm, address, 1, 1);
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}
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static void intel_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm,
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unsigned long address)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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intel_flush_svm_range(svm, address, 1, 1);
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}
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/* Pages have been freed at this point */
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static void intel_invalidate_range(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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intel_flush_svm_range(svm, start,
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(end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT , 0);
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}
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static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev)
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{
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struct qi_desc desc;
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desc.high = 0;
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desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(svm->pasid);
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qi_submit_sync(&desc, svm->iommu);
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}
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static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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svm->iommu->pasid_table[svm->pasid].val = 0;
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/* There's no need to do any flush because we can't get here if there
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* are any devices left anyway. */
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WARN_ON(!list_empty(&svm->devs));
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}
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static const struct mmu_notifier_ops intel_mmuops = {
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.release = intel_mm_release,
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.change_pte = intel_change_pte,
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.invalidate_page = intel_invalidate_page,
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.invalidate_range = intel_invalidate_range,
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};
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static DEFINE_MUTEX(pasid_mutex);
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int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
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{
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struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
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struct intel_svm_dev *sdev;
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struct intel_svm *svm = NULL;
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struct mm_struct *mm = NULL;
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int pasid_max;
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int ret;
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if (WARN_ON(!iommu))
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return -EINVAL;
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if (dev_is_pci(dev)) {
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pasid_max = pci_max_pasids(to_pci_dev(dev));
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if (pasid_max < 0)
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return -EINVAL;
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} else
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pasid_max = 1 << 20;
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if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
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if (!ecap_srs(iommu->ecap))
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return -EINVAL;
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} else if (pasid) {
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mm = get_task_mm(current);
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BUG_ON(!mm);
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}
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mutex_lock(&pasid_mutex);
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if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
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int i;
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idr_for_each_entry(&iommu->pasid_idr, svm, i) {
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if (svm->mm != mm ||
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(svm->flags & SVM_FLAG_PRIVATE_PASID))
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continue;
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if (svm->pasid >= pasid_max) {
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dev_warn(dev,
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"Limited PASID width. Cannot use existing PASID %d\n",
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svm->pasid);
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ret = -ENOSPC;
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goto out;
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}
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list_for_each_entry(sdev, &svm->devs, list) {
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if (dev == sdev->dev) {
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if (sdev->ops != ops) {
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ret = -EBUSY;
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goto out;
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}
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sdev->users++;
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goto success;
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}
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}
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break;
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}
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}
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sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
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if (!sdev) {
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ret = -ENOMEM;
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goto out;
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}
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sdev->dev = dev;
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ret = intel_iommu_enable_pasid(iommu, sdev);
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if (ret || !pasid) {
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/* If they don't actually want to assign a PASID, this is
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* just an enabling check/preparation. */
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kfree(sdev);
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goto out;
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}
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/* Finish the setup now we know we're keeping it */
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sdev->users = 1;
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sdev->ops = ops;
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init_rcu_head(&sdev->rcu);
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if (!svm) {
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svm = kzalloc(sizeof(*svm), GFP_KERNEL);
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if (!svm) {
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ret = -ENOMEM;
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kfree(sdev);
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goto out;
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}
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svm->iommu = iommu;
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if (pasid_max > 2 << ecap_pss(iommu->ecap))
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pasid_max = 2 << ecap_pss(iommu->ecap);
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ret = idr_alloc(&iommu->pasid_idr, svm, 0, pasid_max - 1,
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GFP_KERNEL);
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if (ret < 0) {
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kfree(svm);
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goto out;
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}
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svm->pasid = ret;
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svm->notifier.ops = &intel_mmuops;
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svm->mm = mm;
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svm->flags = flags;
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INIT_LIST_HEAD_RCU(&svm->devs);
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ret = -ENOMEM;
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if (mm) {
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ret = mmu_notifier_register(&svm->notifier, mm);
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if (ret) {
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idr_remove(&svm->iommu->pasid_idr, svm->pasid);
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kfree(svm);
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kfree(sdev);
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goto out;
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}
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iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
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mm = NULL;
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} else
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iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
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wmb();
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}
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list_add_rcu(&sdev->list, &svm->devs);
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success:
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*pasid = svm->pasid;
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ret = 0;
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out:
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mutex_unlock(&pasid_mutex);
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if (mm)
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mmput(mm);
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return ret;
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}
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EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
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int intel_svm_unbind_mm(struct device *dev, int pasid)
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{
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struct intel_svm_dev *sdev;
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struct intel_iommu *iommu;
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struct intel_svm *svm;
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int ret = -EINVAL;
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mutex_lock(&pasid_mutex);
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iommu = intel_svm_device_to_iommu(dev);
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if (!iommu || !iommu->pasid_table)
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goto out;
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svm = idr_find(&iommu->pasid_idr, pasid);
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if (!svm)
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goto out;
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list_for_each_entry(sdev, &svm->devs, list) {
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if (dev == sdev->dev) {
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ret = 0;
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sdev->users--;
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if (!sdev->users) {
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list_del_rcu(&sdev->list);
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/* Flush the PASID cache and IOTLB for this device.
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* Note that we do depend on the hardware *not* using
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* the PASID any more. Just as we depend on other
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* devices never using PASIDs that they have no right
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* to use. We have a *shared* PASID table, because it's
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* large and has to be physically contiguous. So it's
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* hard to be as defensive as we might like. */
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intel_flush_pasid_dev(svm, sdev);
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intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
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kfree_rcu(sdev, rcu);
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if (list_empty(&svm->devs)) {
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mmu_notifier_unregister(&svm->notifier, svm->mm);
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idr_remove(&svm->iommu->pasid_idr, svm->pasid);
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if (svm->mm)
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mmput(svm->mm);
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/* We mandate that no page faults may be outstanding
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* for the PASID when intel_svm_unbind_mm() is called.
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* If that is not obeyed, subtle errors will happen.
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* Let's make them less subtle... */
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memset(svm, 0x6b, sizeof(*svm));
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kfree(svm);
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}
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}
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break;
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}
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}
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out:
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mutex_unlock(&pasid_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
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/* Page request queue descriptor */
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struct page_req_dsc {
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u64 srr:1;
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u64 bof:1;
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u64 pasid_present:1;
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u64 lpig:1;
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u64 pasid:20;
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u64 bus:8;
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u64 private:23;
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u64 prg_index:9;
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u64 rd_req:1;
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u64 wr_req:1;
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u64 exe_req:1;
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u64 priv_req:1;
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u64 devfn:8;
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u64 addr:52;
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};
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#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
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static irqreturn_t prq_event_thread(int irq, void *d)
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{
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struct intel_iommu *iommu = d;
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struct intel_svm *svm = NULL;
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int head, tail, handled = 0;
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|
|
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
|
|
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
|
|
while (head != tail) {
|
|
struct intel_svm_dev *sdev;
|
|
struct vm_area_struct *vma;
|
|
struct page_req_dsc *req;
|
|
struct qi_desc resp;
|
|
int ret, result;
|
|
u64 address;
|
|
|
|
handled = 1;
|
|
|
|
req = &iommu->prq[head / sizeof(*req)];
|
|
|
|
result = QI_RESP_FAILURE;
|
|
address = req->addr << PAGE_SHIFT;
|
|
if (!req->pasid_present) {
|
|
pr_err("%s: Page request without PASID: %08llx %08llx\n",
|
|
iommu->name, ((unsigned long long *)req)[0],
|
|
((unsigned long long *)req)[1]);
|
|
goto bad_req;
|
|
}
|
|
|
|
if (!svm || svm->pasid != req->pasid) {
|
|
rcu_read_lock();
|
|
svm = idr_find(&iommu->pasid_idr, req->pasid);
|
|
/* It *can't* go away, because the driver is not permitted
|
|
* to unbind the mm while any page faults are outstanding.
|
|
* So we only need RCU to protect the internal idr code. */
|
|
rcu_read_unlock();
|
|
|
|
if (!svm) {
|
|
pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
|
|
iommu->name, req->pasid, ((unsigned long long *)req)[0],
|
|
((unsigned long long *)req)[1]);
|
|
goto no_pasid;
|
|
}
|
|
}
|
|
|
|
result = QI_RESP_INVALID;
|
|
/* Since we're using init_mm.pgd directly, we should never take
|
|
* any faults on kernel addresses. */
|
|
if (!svm->mm)
|
|
goto bad_req;
|
|
down_read(&svm->mm->mmap_sem);
|
|
vma = find_extend_vma(svm->mm, address);
|
|
if (!vma || address < vma->vm_start)
|
|
goto invalid;
|
|
|
|
ret = handle_mm_fault(svm->mm, vma, address,
|
|
req->wr_req ? FAULT_FLAG_WRITE : 0);
|
|
if (ret & VM_FAULT_ERROR)
|
|
goto invalid;
|
|
|
|
result = QI_RESP_SUCCESS;
|
|
invalid:
|
|
up_read(&svm->mm->mmap_sem);
|
|
bad_req:
|
|
/* Accounting for major/minor faults? */
|
|
rcu_read_lock();
|
|
list_for_each_entry_rcu(sdev, &svm->devs, list) {
|
|
if (sdev->sid == PCI_DEVID(req->bus, req->devfn));
|
|
break;
|
|
}
|
|
/* Other devices can go away, but the drivers are not permitted
|
|
* to unbind while any page faults might be in flight. So it's
|
|
* OK to drop the 'lock' here now we have it. */
|
|
rcu_read_unlock();
|
|
|
|
if (WARN_ON(&sdev->list == &svm->devs))
|
|
sdev = NULL;
|
|
|
|
if (sdev && sdev->ops && sdev->ops->fault_cb) {
|
|
int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
|
|
(req->wr_req << 1) | (req->exe_req);
|
|
sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
|
|
}
|
|
/* We get here in the error case where the PASID lookup failed,
|
|
and these can be NULL. Do not use them below this point! */
|
|
sdev = NULL;
|
|
svm = NULL;
|
|
no_pasid:
|
|
if (req->lpig) {
|
|
/* Page Group Response */
|
|
resp.low = QI_PGRP_PASID(req->pasid) |
|
|
QI_PGRP_DID((req->bus << 8) | req->devfn) |
|
|
QI_PGRP_PASID_P(req->pasid_present) |
|
|
QI_PGRP_RESP_TYPE;
|
|
resp.high = QI_PGRP_IDX(req->prg_index) |
|
|
QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
|
|
|
|
qi_submit_sync(&resp, iommu);
|
|
} else if (req->srr) {
|
|
/* Page Stream Response */
|
|
resp.low = QI_PSTRM_IDX(req->prg_index) |
|
|
QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
|
|
QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
|
|
resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
|
|
QI_PSTRM_RESP_CODE(result);
|
|
|
|
qi_submit_sync(&resp, iommu);
|
|
}
|
|
|
|
head = (head + sizeof(*req)) & PRQ_RING_MASK;
|
|
}
|
|
|
|
dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
|
|
|
|
return IRQ_RETVAL(handled);
|
|
}
|