Christoph Hellwig 09230cbc1b swiotlb: move the SWIOTLB config symbol to lib/Kconfig ... This way we have one central definition of it, and user can select it as needed. The new option is not user visible, which is the behavior it had in most architectures, with a few notable exceptions: - On x86_64 and mips/loongson3 it used to be user selectable, but defaulted to y. It now is unconditional, which seems like the right thing for 64-bit architectures without guaranteed availablity of IOMMUs. - on powerpc the symbol is user selectable and defaults to n, but many boards select it. This change assumes no working setup required a manual selection, but if that turned out to be wrong we'll have to add another select statement or two for the respective boards. Signed-off-by: Christoph Hellwig <hch@lst.de>		2018-05-09 06:58:01 +02:00
..
alignment.c	sched/headers: Prepare for new header dependencies before moving code to <linux/sched/debug.h>	2017-03-02 08:42:34 +01:00
cache-ucv2.S	unicore32 core architecture: mm related: consistent device DMA handling	2011-03-17 09:19:09 +08:00
extable.c	unicore32: migrate exception table users off module.h and onto extable.h	2017-01-26 10:58:18 -05:00
fault.c	sched/headers: Prepare for new header dependencies before moving code to <linux/sched/signal.h>	2017-03-02 08:42:29 +01:00
flush.c	mm: fix races between swapoff and flush dcache	2018-04-05 21:36:26 -07:00
init.c	arch, mm: remove arch specific show_mem	2017-02-22 16:41:30 -08:00
ioremap.c	arch/unicore32/mm/ioremap.c: return NULL on invalid pfn	2014-06-04 16:53:53 -07:00
Kconfig	swiotlb: move the SWIOTLB config symbol to lib/Kconfig	2018-05-09 06:58:01 +02:00
Makefile	unicore32: use generic swiotlb_ops	2018-01-15 09:35:55 +01:00
mm.h	Disintegrate asm/system.h for Unicore32 [based on ver #3, changed by gxt]	2012-03-28 18:30:03 +01:00
mmu.c	mm: fix races between swapoff and flush dcache	2018-04-05 21:36:26 -07:00
pgd.c	mm: introduce wrappers to access mm->nr_ptes	2017-11-15 18:21:04 -08:00
proc-macros.S
proc-syms.c	unicore32: make dma_cache_sync a no-op	2017-10-19 16:37:36 +02:00
proc-ucv2.S
tlb-ucv2.S	unicore32 core architecture: mm related: consistent device DMA handling	2011-03-17 09:19:09 +08:00