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26e5157133
Add driver for the PCI Express Downstream Port Containment extended capability. DPC is an optional capability to contain uncorrectable errors below a port. For more information on DPC, please see PCI Express Base Specification Revision 4, section 7.31, or view the PCI-SIG DPC ECN here: https://pcisig.com/sites/default/files/specification_documents/ECN_DPC_2012-02-09_finalized.pdf When a DPC event is triggered, the hardware disables downstream links, so the DPC driver schedules removal for all devices below this port. This may happen concurrently with a PCIe hotplug driver if enabled. When all downstream devices are removed and the link state transitions to disabled, the DPC driver clears the DPC status and interrupt bits so the link may retrain for a newly connected device. [bhelgaas: clear (not set) DPC_CTL bits on remove, whitespace cleanup] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lukas Wunner <lukas@wunner.de> |
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| asm-generic | ||
| clocksource | ||
| crypto | ||
| drm | ||
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| keys | ||
| kvm | ||
| linux | ||
| math-emu | ||
| media | ||
| memory | ||
| misc | ||
| net | ||
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| ras | ||
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| soc | ||
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| target | ||
| trace | ||
| uapi | ||
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| xen | ||
| Kbuild | ||