Thierry Reding 26f8590c4a clk: tegra: Make vic03 a child of pll_c3 ... By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2018-07-08 17:03:59 -07:00
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clk-audio-sync.c	clk: tegra: Remove CLK_IS_ROOT	2016-03-02 17:47:19 -08:00
clk-bpmp.c	clk: tegra: Check BPMP response return code	2017-10-19 16:38:40 +02:00
clk-dfll.c	clk: tegra: no need to check return value of debugfs_create functions	2018-06-01 19:25:51 -07:00
clk-dfll.h	clk: tegra: dfll: Fix drvdata overwriting issue	2017-11-01 15:00:06 +01:00
clk-divider.c	tegra/clk-divider: fix wrong do_div() usage	2015-11-16 12:37:55 -05:00
clk-emc.c	clk: tegra: Mark HCLK, SCLK and EMC as critical	2018-03-12 13:58:58 +01:00
clk-id.h	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
clk-periph-fixed.c	clk: tegra: Add fixed factor peripheral clock type	2016-04-28 12:41:47 +02:00
clk-periph-gate.c	clk: tegra: Fix disable unused for clocks sharing enable bit	2017-03-20 14:13:52 +01:00
clk-periph.c	clk: tegra: Add peripheral clock registration helper	2017-10-19 16:38:40 +02:00
clk-pll-out.c	clk: tegra: Properly include clk.h	2015-07-20 11:11:17 -07:00
clk-pll.c	clk: tegra: Fix pll_u rate configuration	2018-03-12 13:59:06 +01:00
clk-super.c	clk: tegra: Add super clock mux/divider	2017-03-20 14:07:33 +01:00
clk-tegra-audio.c	clk: tegra: Define Tegra210 DMIC sync clocks	2017-03-20 14:06:33 +01:00
clk-tegra-fixed.c	clk: tegra: Remove trailing blank line	2016-04-28 12:41:45 +02:00
clk-tegra-periph.c	clk: tegra: Mark HCLK, SCLK and EMC as critical	2018-03-12 13:58:58 +01:00
clk-tegra-pmc.c	clk: tegra: Propagate clk_out_x rate to parent	2017-04-04 16:00:28 +02:00
clk-tegra-super-gen4.c	clk: tegra: Mark HCLK, SCLK and EMC as critical	2018-03-12 13:58:58 +01:00
clk-tegra20.c	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	2018-05-18 12:35:28 +02:00
clk-tegra30.c	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	2018-05-18 12:35:28 +02:00
clk-tegra114.c	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	2018-05-18 12:35:28 +02:00
clk-tegra124-dfll-fcpu.c	clk: tegra: dfll: Fix drvdata overwriting issue	2017-11-01 15:00:06 +01:00
clk-tegra124.c	clk: tegra: Make vic03 a child of pll_c3	2018-07-08 17:03:59 -07:00
clk-tegra210.c	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	2018-05-18 12:35:28 +02:00
clk.c	treewide: kzalloc() -> kcalloc()	2018-06-12 16:19:22 -07:00
clk.h	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	2018-05-18 12:35:28 +02:00
cvb.c	clk: tegra: dfll: improve function-level documentation	2016-11-01 17:38:50 -07:00
cvb.h	clk: tegra: dfll: Properly clean up on failure and removal	2016-04-28 12:41:54 +02:00
Kconfig	clk: tegra: Add BPMP clock driver	2017-02-03 12:36:36 -08:00
Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00