Sumit Gupta b713442214 soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 ... Adding driver to handle errors from Control Backbone (CBB) which are generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs. When an error is reported from a NOC within CBB, the driver prints debug information about failed transaction like Error Code, Error Description, Master, Address, AXI ID, Cache, Protection, Security Group etc. It then causes system crash using BUG_ON() or call WARN() based on whether the error type is fatal or not. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2022-09-15 12:41:36 +02:00
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ahb.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
bpmp-abi.h	soc/tegra: bpmp: cleanup double word in comment	2022-02-25 14:10:09 +01:00
bpmp.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
common.h	soc/tegra: Add devm_tegra_core_dev_init_opp_table_common()	2021-12-16 14:03:38 +01:00
cpuidle.h	cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle	2020-03-13 11:31:58 +01:00
flowctrl.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 399	2019-06-05 17:37:12 +02:00
fuse.h	soc/tegra: Set ERD bit to mask inband errors	2022-09-15 12:30:11 +02:00
irq.h	soc/tegra: irq: Add stubs needed for compile testing	2021-10-04 21:27:21 +02:00
ivc.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
mc.h	memory: tegra: Add MC error logging on Tegra186 onward	2022-05-09 10:46:14 +02:00
pm.h	soc/tegra: pm: Make stubs usable for compile testing	2021-10-04 21:27:40 +02:00
pmc.h	soc/tegra: pmc: Add driver state syncing	2021-06-02 10:58:55 +02:00
tegra-cbb.h	soc/tegra: cbb: Add CBB 1.0 driver for Tegra194	2022-09-15 12:41:36 +02:00