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27d4f2c654
Use devm_ variants of kzalloc and ioremap. Also clean up error path. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
677 lines
18 KiB
C
677 lines
18 KiB
C
/**
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* omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
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* Author: Keshava Munegowda <keshava_mgowda@ti.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/usb-omap.h>
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#include <linux/pm_runtime.h>
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#include "omap-usb.h"
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#define USBHS_DRIVER_NAME "usbhs_omap"
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#define OMAP_EHCI_DEVICE "ehci-omap"
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#define OMAP_OHCI_DEVICE "ohci-omap3"
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/* OMAP USBHOST Register addresses */
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/* UHH Register Set */
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#define OMAP_UHH_REVISION (0x00)
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#define OMAP_UHH_SYSCONFIG (0x10)
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#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
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#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
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#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
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#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
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#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
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#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
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#define OMAP_UHH_SYSSTATUS (0x14)
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#define OMAP_UHH_HOSTCONFIG (0x40)
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#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
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#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
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#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
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#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
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#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
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#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
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#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
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#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
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#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
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#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
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#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
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#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
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/* OMAP4-specific defines */
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#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
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#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
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#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
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#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
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#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
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#define OMAP4_P1_MODE_CLEAR (3 << 16)
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#define OMAP4_P1_MODE_TLL (1 << 16)
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#define OMAP4_P1_MODE_HSIC (3 << 16)
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#define OMAP4_P2_MODE_CLEAR (3 << 18)
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#define OMAP4_P2_MODE_TLL (1 << 18)
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#define OMAP4_P2_MODE_HSIC (3 << 18)
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#define OMAP_UHH_DEBUG_CSR (0x44)
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/* Values of UHH_REVISION - Note: these are not given in the TRM */
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#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
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#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
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#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
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#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
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#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
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#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
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#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
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struct usbhs_hcd_omap {
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struct clk *xclk60mhsp1_ck;
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struct clk *xclk60mhsp2_ck;
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struct clk *utmi_p1_fck;
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struct clk *usbhost_p1_fck;
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struct clk *utmi_p2_fck;
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struct clk *usbhost_p2_fck;
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struct clk *init_60m_fclk;
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struct clk *ehci_logic_fck;
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void __iomem *uhh_base;
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struct usbhs_omap_platform_data *pdata;
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u32 usbhs_rev;
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spinlock_t lock;
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};
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/*-------------------------------------------------------------------------*/
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const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
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static u64 usbhs_dmamask = DMA_BIT_MASK(32);
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/*-------------------------------------------------------------------------*/
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static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
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{
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__raw_writel(val, base + reg);
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}
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static inline u32 usbhs_read(void __iomem *base, u32 reg)
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{
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return __raw_readl(base + reg);
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}
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static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
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{
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__raw_writeb(val, base + reg);
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}
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static inline u8 usbhs_readb(void __iomem *base, u8 reg)
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{
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return __raw_readb(base + reg);
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}
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/*-------------------------------------------------------------------------*/
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static struct platform_device *omap_usbhs_alloc_child(const char *name,
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struct resource *res, int num_resources, void *pdata,
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size_t pdata_size, struct device *dev)
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{
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struct platform_device *child;
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int ret;
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child = platform_device_alloc(name, 0);
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if (!child) {
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dev_err(dev, "platform_device_alloc %s failed\n", name);
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goto err_end;
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}
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ret = platform_device_add_resources(child, res, num_resources);
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if (ret) {
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dev_err(dev, "platform_device_add_resources failed\n");
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goto err_alloc;
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}
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ret = platform_device_add_data(child, pdata, pdata_size);
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if (ret) {
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dev_err(dev, "platform_device_add_data failed\n");
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goto err_alloc;
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}
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child->dev.dma_mask = &usbhs_dmamask;
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dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
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child->dev.parent = dev;
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ret = platform_device_add(child);
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if (ret) {
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dev_err(dev, "platform_device_add failed\n");
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goto err_alloc;
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}
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return child;
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err_alloc:
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platform_device_put(child);
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err_end:
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return NULL;
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}
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static int omap_usbhs_alloc_children(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct usbhs_omap_platform_data *pdata = dev->platform_data;
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struct platform_device *ehci;
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struct platform_device *ohci;
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struct resource *res;
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struct resource resources[2];
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int ret;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
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if (!res) {
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dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
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ret = -ENODEV;
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goto err_end;
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}
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resources[0] = *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
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if (!res) {
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dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
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ret = -ENODEV;
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goto err_end;
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}
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resources[1] = *res;
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ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
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sizeof(*pdata), dev);
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if (!ehci) {
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dev_err(dev, "omap_usbhs_alloc_child failed\n");
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ret = -ENOMEM;
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goto err_end;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
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if (!res) {
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dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
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ret = -ENODEV;
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goto err_ehci;
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}
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resources[0] = *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
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if (!res) {
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dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
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ret = -ENODEV;
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goto err_ehci;
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}
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resources[1] = *res;
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ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
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sizeof(*pdata), dev);
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if (!ohci) {
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dev_err(dev, "omap_usbhs_alloc_child failed\n");
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ret = -ENOMEM;
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goto err_ehci;
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}
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return 0;
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err_ehci:
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platform_device_unregister(ehci);
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err_end:
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return ret;
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}
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static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
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{
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switch (pmode) {
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case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
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case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
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case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
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case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
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case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
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case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
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case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
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case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
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case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
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case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
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return true;
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default:
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return false;
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}
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}
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static int usbhs_runtime_resume(struct device *dev)
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{
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struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
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struct usbhs_omap_platform_data *pdata = omap->pdata;
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unsigned long flags;
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dev_dbg(dev, "usbhs_runtime_resume\n");
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omap_tll_enable();
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spin_lock_irqsave(&omap->lock, flags);
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if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
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clk_enable(omap->ehci_logic_fck);
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if (is_ehci_tll_mode(pdata->port_mode[0]))
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clk_enable(omap->usbhost_p1_fck);
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if (is_ehci_tll_mode(pdata->port_mode[1]))
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clk_enable(omap->usbhost_p2_fck);
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clk_enable(omap->utmi_p1_fck);
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clk_enable(omap->utmi_p2_fck);
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spin_unlock_irqrestore(&omap->lock, flags);
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return 0;
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}
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static int usbhs_runtime_suspend(struct device *dev)
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{
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struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
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struct usbhs_omap_platform_data *pdata = omap->pdata;
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unsigned long flags;
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dev_dbg(dev, "usbhs_runtime_suspend\n");
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spin_lock_irqsave(&omap->lock, flags);
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if (is_ehci_tll_mode(pdata->port_mode[0]))
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clk_disable(omap->usbhost_p1_fck);
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if (is_ehci_tll_mode(pdata->port_mode[1]))
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clk_disable(omap->usbhost_p2_fck);
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clk_disable(omap->utmi_p2_fck);
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clk_disable(omap->utmi_p1_fck);
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if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
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clk_disable(omap->ehci_logic_fck);
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spin_unlock_irqrestore(&omap->lock, flags);
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omap_tll_disable();
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return 0;
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}
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static void omap_usbhs_init(struct device *dev)
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{
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struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
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struct usbhs_omap_platform_data *pdata = omap->pdata;
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unsigned long flags;
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unsigned reg;
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dev_dbg(dev, "starting TI HSUSB Controller\n");
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if (pdata->phy_reset) {
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if (gpio_is_valid(pdata->reset_gpio_port[0]))
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gpio_request_one(pdata->reset_gpio_port[0],
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GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
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if (gpio_is_valid(pdata->reset_gpio_port[1]))
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gpio_request_one(pdata->reset_gpio_port[1],
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GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
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/* Hold the PHY in RESET for enough time till DIR is high */
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udelay(10);
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}
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pm_runtime_get_sync(dev);
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spin_lock_irqsave(&omap->lock, flags);
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omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
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dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
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reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
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/* setup ULPI bypass and burst configurations */
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reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
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| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
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| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
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reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
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reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
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if (is_omap_usbhs_rev1(omap)) {
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if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
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reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
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if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
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reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
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if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
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reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
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/* Bypass the TLL module for PHY mode operation */
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if (pdata->single_ulpi_bypass) {
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dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
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if (is_ehci_phy_mode(pdata->port_mode[0]) ||
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is_ehci_phy_mode(pdata->port_mode[1]) ||
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is_ehci_phy_mode(pdata->port_mode[2]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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else
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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} else {
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dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
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if (is_ehci_phy_mode(pdata->port_mode[0]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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else
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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if (is_ehci_phy_mode(pdata->port_mode[1]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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else
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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if (is_ehci_phy_mode(pdata->port_mode[2]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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else
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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}
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} else if (is_omap_usbhs_rev2(omap)) {
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/* Clear port mode fields for PHY mode*/
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reg &= ~OMAP4_P1_MODE_CLEAR;
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reg &= ~OMAP4_P2_MODE_CLEAR;
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if (is_ehci_tll_mode(pdata->port_mode[0]) ||
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(is_ohci_port(pdata->port_mode[0])))
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reg |= OMAP4_P1_MODE_TLL;
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else if (is_ehci_hsic_mode(pdata->port_mode[0]))
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reg |= OMAP4_P1_MODE_HSIC;
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if (is_ehci_tll_mode(pdata->port_mode[1]) ||
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(is_ohci_port(pdata->port_mode[1])))
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reg |= OMAP4_P2_MODE_TLL;
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else if (is_ehci_hsic_mode(pdata->port_mode[1]))
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reg |= OMAP4_P2_MODE_HSIC;
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}
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usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
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dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
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spin_unlock_irqrestore(&omap->lock, flags);
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pm_runtime_put_sync(dev);
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if (pdata->phy_reset) {
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/* Hold the PHY in RESET for enough time till
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* PHY is settled and ready
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*/
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udelay(10);
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if (gpio_is_valid(pdata->reset_gpio_port[0]))
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gpio_set_value_cansleep
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(pdata->reset_gpio_port[0], 1);
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if (gpio_is_valid(pdata->reset_gpio_port[1]))
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gpio_set_value_cansleep
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(pdata->reset_gpio_port[1], 1);
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}
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}
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static void omap_usbhs_deinit(struct device *dev)
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{
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struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
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struct usbhs_omap_platform_data *pdata = omap->pdata;
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|
|
if (pdata->phy_reset) {
|
|
if (gpio_is_valid(pdata->reset_gpio_port[0]))
|
|
gpio_free(pdata->reset_gpio_port[0]);
|
|
|
|
if (gpio_is_valid(pdata->reset_gpio_port[1]))
|
|
gpio_free(pdata->reset_gpio_port[1]);
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* usbhs_omap_probe - initialize TI-based HCDs
|
|
*
|
|
* Allocates basic resources for this USB host controller.
|
|
*/
|
|
static int usbhs_omap_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct usbhs_omap_platform_data *pdata = dev->platform_data;
|
|
struct usbhs_hcd_omap *omap;
|
|
struct resource *res;
|
|
int ret = 0;
|
|
int i;
|
|
|
|
if (!pdata) {
|
|
dev_err(dev, "Missing platform data\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
|
|
if (!omap) {
|
|
dev_err(dev, "Memory allocation failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
|
|
omap->uhh_base = devm_request_and_ioremap(dev, res);
|
|
if (!omap->uhh_base) {
|
|
dev_err(dev, "Resource request/ioremap failed\n");
|
|
return -EADDRNOTAVAIL;
|
|
}
|
|
|
|
spin_lock_init(&omap->lock);
|
|
|
|
omap->pdata = pdata;
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
|
|
if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
|
|
is_ehci_hsic_mode(i)) {
|
|
omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
|
|
if (IS_ERR(omap->ehci_logic_fck)) {
|
|
ret = PTR_ERR(omap->ehci_logic_fck);
|
|
dev_warn(dev, "ehci_logic_fck failed:%d\n",
|
|
ret);
|
|
}
|
|
break;
|
|
}
|
|
|
|
omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
|
|
if (IS_ERR(omap->utmi_p1_fck)) {
|
|
ret = PTR_ERR(omap->utmi_p1_fck);
|
|
dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
|
|
goto err_end;
|
|
}
|
|
|
|
omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
|
|
if (IS_ERR(omap->xclk60mhsp1_ck)) {
|
|
ret = PTR_ERR(omap->xclk60mhsp1_ck);
|
|
dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
|
|
goto err_utmi_p1_fck;
|
|
}
|
|
|
|
omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
|
|
if (IS_ERR(omap->utmi_p2_fck)) {
|
|
ret = PTR_ERR(omap->utmi_p2_fck);
|
|
dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
|
|
goto err_xclk60mhsp1_ck;
|
|
}
|
|
|
|
omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
|
|
if (IS_ERR(omap->xclk60mhsp2_ck)) {
|
|
ret = PTR_ERR(omap->xclk60mhsp2_ck);
|
|
dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
|
|
goto err_utmi_p2_fck;
|
|
}
|
|
|
|
omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
|
|
if (IS_ERR(omap->usbhost_p1_fck)) {
|
|
ret = PTR_ERR(omap->usbhost_p1_fck);
|
|
dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
|
|
goto err_xclk60mhsp2_ck;
|
|
}
|
|
|
|
omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
|
|
if (IS_ERR(omap->usbhost_p2_fck)) {
|
|
ret = PTR_ERR(omap->usbhost_p2_fck);
|
|
dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
|
|
goto err_usbhost_p1_fck;
|
|
}
|
|
|
|
omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
|
|
if (IS_ERR(omap->init_60m_fclk)) {
|
|
ret = PTR_ERR(omap->init_60m_fclk);
|
|
dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
|
|
goto err_usbhost_p2_fck;
|
|
}
|
|
|
|
if (is_ehci_phy_mode(pdata->port_mode[0])) {
|
|
/* for OMAP3 , the clk set paretn fails */
|
|
ret = clk_set_parent(omap->utmi_p1_fck,
|
|
omap->xclk60mhsp1_ck);
|
|
if (ret != 0)
|
|
dev_err(dev, "xclk60mhsp1_ck set parent"
|
|
"failed error:%d\n", ret);
|
|
} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
|
|
ret = clk_set_parent(omap->utmi_p1_fck,
|
|
omap->init_60m_fclk);
|
|
if (ret != 0)
|
|
dev_err(dev, "init_60m_fclk set parent"
|
|
"failed error:%d\n", ret);
|
|
}
|
|
|
|
if (is_ehci_phy_mode(pdata->port_mode[1])) {
|
|
ret = clk_set_parent(omap->utmi_p2_fck,
|
|
omap->xclk60mhsp2_ck);
|
|
if (ret != 0)
|
|
dev_err(dev, "xclk60mhsp2_ck set parent"
|
|
"failed error:%d\n", ret);
|
|
} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
|
|
ret = clk_set_parent(omap->utmi_p2_fck,
|
|
omap->init_60m_fclk);
|
|
if (ret != 0)
|
|
dev_err(dev, "init_60m_fclk set parent"
|
|
"failed error:%d\n", ret);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, omap);
|
|
|
|
omap_usbhs_init(dev);
|
|
ret = omap_usbhs_alloc_children(pdev);
|
|
if (ret) {
|
|
dev_err(dev, "omap_usbhs_alloc_children failed\n");
|
|
goto err_alloc;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_alloc:
|
|
omap_usbhs_deinit(&pdev->dev);
|
|
clk_put(omap->init_60m_fclk);
|
|
|
|
err_usbhost_p2_fck:
|
|
clk_put(omap->usbhost_p2_fck);
|
|
|
|
err_usbhost_p1_fck:
|
|
clk_put(omap->usbhost_p1_fck);
|
|
|
|
err_xclk60mhsp2_ck:
|
|
clk_put(omap->xclk60mhsp2_ck);
|
|
|
|
err_utmi_p2_fck:
|
|
clk_put(omap->utmi_p2_fck);
|
|
|
|
err_xclk60mhsp1_ck:
|
|
clk_put(omap->xclk60mhsp1_ck);
|
|
|
|
err_utmi_p1_fck:
|
|
clk_put(omap->utmi_p1_fck);
|
|
|
|
err_end:
|
|
clk_put(omap->ehci_logic_fck);
|
|
pm_runtime_disable(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
|
|
* @pdev: USB Host Controller being removed
|
|
*
|
|
* Reverses the effect of usbhs_omap_probe().
|
|
*/
|
|
static int usbhs_omap_remove(struct platform_device *pdev)
|
|
{
|
|
struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
|
|
|
|
omap_usbhs_deinit(&pdev->dev);
|
|
clk_put(omap->init_60m_fclk);
|
|
clk_put(omap->usbhost_p2_fck);
|
|
clk_put(omap->usbhost_p1_fck);
|
|
clk_put(omap->xclk60mhsp2_ck);
|
|
clk_put(omap->utmi_p2_fck);
|
|
clk_put(omap->xclk60mhsp1_ck);
|
|
clk_put(omap->utmi_p1_fck);
|
|
clk_put(omap->ehci_logic_fck);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
|
|
.runtime_suspend = usbhs_runtime_suspend,
|
|
.runtime_resume = usbhs_runtime_resume,
|
|
};
|
|
|
|
static struct platform_driver usbhs_omap_driver = {
|
|
.driver = {
|
|
.name = (char *)usbhs_driver_name,
|
|
.owner = THIS_MODULE,
|
|
.pm = &usbhsomap_dev_pm_ops,
|
|
},
|
|
.remove = __exit_p(usbhs_omap_remove),
|
|
};
|
|
|
|
MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
|
|
MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
|
|
|
|
static int __init omap_usbhs_drvinit(void)
|
|
{
|
|
return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
|
|
}
|
|
|
|
/*
|
|
* init before ehci and ohci drivers;
|
|
* The usbhs core driver should be initialized much before
|
|
* the omap ehci and ohci probe functions are called.
|
|
* This usbhs core driver should be initialized after
|
|
* usb tll driver
|
|
*/
|
|
fs_initcall_sync(omap_usbhs_drvinit);
|
|
|
|
static void __exit omap_usbhs_drvexit(void)
|
|
{
|
|
platform_driver_unregister(&usbhs_omap_driver);
|
|
}
|
|
module_exit(omap_usbhs_drvexit);
|