Leo (Hanghong) Ma 28fa24ad14 drm/amd/display: Change the delay time before enabling FEC ... [why] DP spec requires 1000 symbols delay between the end of link training and enabling FEC in the stream. Currently we are using 1 miliseconds delay which is not accurate. [how] One lane RBR should have the maximum time for transmitting 1000 LL codes which is 6.173 us. So using 7 microseconds delay instead of 1 miliseconds. Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-12-05 18:18:33 -05:00
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drm	drm/amd/display: Change the delay time before enabling FEC	2019-12-05 18:18:33 -05:00
host1x	gpu: host1x: Unconditionally select IOMMU_IOVA	2019-11-01 10:49:17 +01:00
ipu-v3
vga
Makefile