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c6ca7616f7
Add a clock provider driver for the Canaan Kendryte K210 RISC-V SoC. This new driver with the compatible string "canaan,k210-clk" implements support for the full clock structure of the K210 SoC. Since it is required for the correct operation of the SoC, this driver is selected by default for compilation when the SOC_CANAAN option is selected. With this change, the k210-sysctl driver is turned into a simple platform driver which enables its power bus clock and triggers populating its child nodes. The sysctl driver retains the SOC early initialization code, but the implementation now relies on the new function k210_clk_early_init() provided by the new clk-k210 driver. The clock structure implemented and many of the coding ideas for the driver come from the work by Sean Anderson on the K210 support for the U-Boot project. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
43 lines
2 KiB
C
43 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*/
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#ifndef K210_SYSCTL_H
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#define K210_SYSCTL_H
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/*
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* Kendryte K210 SoC system controller registers offsets.
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* Taken from Kendryte SDK (kendryte-standalone-sdk).
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*/
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#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */
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#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */
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#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */
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#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */
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#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
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#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */
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#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */
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#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */
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#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */
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#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */
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#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */
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#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */
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#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */
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#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */
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#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */
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#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */
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#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */
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#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */
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#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */
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#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */
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#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */
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#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */
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#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */
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#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */
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#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */
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#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */
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#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */
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void k210_clk_early_init(void __iomem *regs);
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#endif
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