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778fb10ccc
Add support for the STORE CPU COUNTER MULTIPLE instruction to extract a range of counters from a counter set. An assembler macro is used to create the instruction opcode because the counter set identifier is part of the instruction and, thus, cannot be easily specified as parameter. Signed-off-by: Hendrik Brueckner <brueckner@linux.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
22 lines
478 B
C
22 lines
478 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for CPU-MF instructions
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*
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* Copyright IBM Corp. 2019
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* Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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*/
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#ifndef _ASM_S390_CPU_MF_INSN_H
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#define _ASM_S390_CPU_MF_INSN_H
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#ifdef __ASSEMBLY__
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/* Macro to generate the STCCTM instruction with a customized
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* M3 field designating the counter set.
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*/
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.macro STCCTM r1 m3 db2
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.insn rsy,0xeb0000000017,\r1,\m3 & 0xf,\db2
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.endm
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#endif /* __ASSEMBLY__ */
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#endif
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