98 lines
2.9 KiB
C
98 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_S390_PCI_DMA_H
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#define _ASM_S390_PCI_DMA_H
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/* I/O Translation Anchor (IOTA) */
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enum zpci_ioat_dtype {
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ZPCI_IOTA_STO = 0,
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ZPCI_IOTA_RTTO = 1,
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ZPCI_IOTA_RSTO = 2,
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ZPCI_IOTA_RFTO = 3,
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ZPCI_IOTA_PFAA = 4,
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ZPCI_IOTA_IOPFAA = 5,
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ZPCI_IOTA_IOPTO = 7
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};
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#define ZPCI_IOTA_IOT_ENABLED 0x800UL
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#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
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#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
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#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
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#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
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#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
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#define ZPCI_IOTA_FS_4K 0
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#define ZPCI_IOTA_FS_1M 1
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#define ZPCI_IOTA_FS_2G 2
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#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
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#define ZPCI_TABLE_SIZE_RT (1UL << 42)
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#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
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#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
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#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
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#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
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#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
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/* I/O Region and segment tables */
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#define ZPCI_INDEX_MASK 0x7ffUL
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#define ZPCI_TABLE_TYPE_MASK 0xc
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#define ZPCI_TABLE_TYPE_RFX 0xc
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#define ZPCI_TABLE_TYPE_RSX 0x8
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#define ZPCI_TABLE_TYPE_RTX 0x4
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#define ZPCI_TABLE_TYPE_SX 0x0
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#define ZPCI_TABLE_LEN_RFX 0x3
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#define ZPCI_TABLE_LEN_RSX 0x3
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#define ZPCI_TABLE_LEN_RTX 0x3
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#define ZPCI_TABLE_OFFSET_MASK 0xc0
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#define ZPCI_TABLE_SIZE 0x4000
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#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
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#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
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#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
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#define ZPCI_TABLE_BITS 11
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#define ZPCI_PT_BITS 8
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#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
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#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
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#define ZPCI_RTE_FLAG_MASK 0x3fffUL
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#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
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#define ZPCI_STE_FLAG_MASK 0x7ffUL
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#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
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/* I/O Page tables */
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#define ZPCI_PTE_VALID_MASK 0x400
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#define ZPCI_PTE_INVALID 0x400
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#define ZPCI_PTE_VALID 0x000
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#define ZPCI_PT_SIZE 0x800
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#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
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#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
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#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
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#define ZPCI_PTE_FLAG_MASK 0xfffUL
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#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
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/* Shared bits */
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#define ZPCI_TABLE_VALID 0x00
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#define ZPCI_TABLE_INVALID 0x20
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#define ZPCI_TABLE_PROTECTED 0x200
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#define ZPCI_TABLE_UNPROTECTED 0x000
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#define ZPCI_TABLE_VALID_MASK 0x20
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#define ZPCI_TABLE_PROT_MASK 0x200
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struct zpci_iommu_ctrs {
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atomic64_t mapped_pages;
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atomic64_t unmapped_pages;
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atomic64_t global_rpcits;
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atomic64_t sync_map_rpcits;
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atomic64_t sync_rpcits;
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};
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struct zpci_dev;
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struct zpci_iommu_ctrs *zpci_get_iommu_ctrs(struct zpci_dev *zdev);
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#endif
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