506 lines
14 KiB
C
506 lines
14 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_ras.h"
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#include "amdgpu.h"
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#include "amdgpu_mca.h"
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#include "umc/umc_6_7_0_offset.h"
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#include "umc/umc_6_7_0_sh_mask.h"
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void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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unsigned long *error_count)
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{
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uint64_t mc_status = RREG64_PCIE(mc_status_addr);
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if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
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*error_count += 1;
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}
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void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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unsigned long *error_count)
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{
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uint64_t mc_status = RREG64_PCIE(mc_status_addr);
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if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
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*error_count += 1;
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}
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void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr)
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{
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WREG64_PCIE(mc_status_addr, 0x0ULL);
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}
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void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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amdgpu_mca_query_correctable_error_count(adev, mc_status_addr, &(err_data->ce_count));
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amdgpu_mca_query_uncorrectable_error_count(adev, mc_status_addr, &(err_data->ue_count));
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amdgpu_mca_reset_error_count(adev, mc_status_addr);
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}
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int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev)
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{
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int err;
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struct amdgpu_mca_ras_block *ras;
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if (!adev->mca.mp0.ras)
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return 0;
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ras = adev->mca.mp0.ras;
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err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
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if (err) {
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dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n");
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return err;
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}
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strcpy(ras->ras_block.ras_comm.name, "mca.mp0");
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ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
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ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->mca.mp0.ras_if = &ras->ras_block.ras_comm;
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return 0;
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}
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int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev)
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{
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int err;
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struct amdgpu_mca_ras_block *ras;
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if (!adev->mca.mp1.ras)
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return 0;
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ras = adev->mca.mp1.ras;
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err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
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if (err) {
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dev_err(adev->dev, "Failed to register mca.mp1 ras block!\n");
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return err;
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}
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strcpy(ras->ras_block.ras_comm.name, "mca.mp1");
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ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
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ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->mca.mp1.ras_if = &ras->ras_block.ras_comm;
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return 0;
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}
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int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev)
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{
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int err;
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struct amdgpu_mca_ras_block *ras;
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if (!adev->mca.mpio.ras)
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return 0;
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ras = adev->mca.mpio.ras;
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err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
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if (err) {
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dev_err(adev->dev, "Failed to register mca.mpio ras block!\n");
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return err;
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}
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strcpy(ras->ras_block.ras_comm.name, "mca.mpio");
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ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
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ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->mca.mpio.ras_if = &ras->ras_block.ras_comm;
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return 0;
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}
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void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set)
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{
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if (!mca_set)
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return;
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memset(mca_set, 0, sizeof(*mca_set));
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INIT_LIST_HEAD(&mca_set->list);
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}
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int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry)
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{
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struct mca_bank_node *node;
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if (!entry)
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return -EINVAL;
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node = kvzalloc(sizeof(*node), GFP_KERNEL);
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if (!node)
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return -ENOMEM;
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memcpy(&node->entry, entry, sizeof(*entry));
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INIT_LIST_HEAD(&node->node);
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list_add_tail(&node->node, &mca_set->list);
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mca_set->nr_entries++;
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return 0;
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}
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void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set)
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{
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struct mca_bank_node *node, *tmp;
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list_for_each_entry_safe(node, tmp, &mca_set->list, node) {
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list_del(&node->node);
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kvfree(node);
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}
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}
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void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs)
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{
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struct amdgpu_mca *mca = &adev->mca;
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mca->mca_funcs = mca_funcs;
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}
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int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
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{
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const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
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if (mca_funcs && mca_funcs->mca_set_debug_mode)
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return mca_funcs->mca_set_debug_mode(adev, enable);
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return -EOPNOTSUPP;
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}
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static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry)
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{
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dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture events logged\n");
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dev_info(adev->dev, "[Hardware error] aca entry[%02d].STATUS=0x%016llx\n",
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idx, entry->regs[MCA_REG_IDX_STATUS]);
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dev_info(adev->dev, "[Hardware error] aca entry[%02d].ADDR=0x%016llx\n",
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idx, entry->regs[MCA_REG_IDX_ADDR]);
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dev_info(adev->dev, "[Hardware error] aca entry[%02d].MISC0=0x%016llx\n",
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idx, entry->regs[MCA_REG_IDX_MISC0]);
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dev_info(adev->dev, "[Hardware error] aca entry[%02d].IPID=0x%016llx\n",
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idx, entry->regs[MCA_REG_IDX_IPID]);
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dev_info(adev->dev, "[Hardware error] aca entry[%02d].SYND=0x%016llx\n",
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idx, entry->regs[MCA_REG_IDX_SYND]);
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}
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int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data)
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{
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struct amdgpu_smuio_mcm_config_info mcm_info;
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struct ras_err_addr err_addr = {0};
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struct mca_bank_set mca_set;
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struct mca_bank_node *node;
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struct mca_bank_entry *entry;
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uint32_t count;
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int ret, i = 0;
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amdgpu_mca_bank_set_init(&mca_set);
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ret = amdgpu_mca_smu_get_mca_set(adev, blk, type, &mca_set);
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if (ret)
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goto out_mca_release;
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list_for_each_entry(node, &mca_set.list, node) {
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entry = &node->entry;
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amdgpu_mca_smu_mca_bank_dump(adev, i++, entry);
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count = 0;
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ret = amdgpu_mca_smu_parse_mca_error_count(adev, blk, type, entry, &count);
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if (ret)
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goto out_mca_release;
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if (!count)
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continue;
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mcm_info.socket_id = entry->info.socket_id;
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mcm_info.die_id = entry->info.aid;
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if (blk == AMDGPU_RAS_BLOCK__UMC) {
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err_addr.err_status = entry->regs[MCA_REG_IDX_STATUS];
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err_addr.err_ipid = entry->regs[MCA_REG_IDX_IPID];
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err_addr.err_addr = entry->regs[MCA_REG_IDX_ADDR];
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}
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if (type == AMDGPU_MCA_ERROR_TYPE_UE)
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amdgpu_ras_error_statistic_ue_count(err_data,
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&mcm_info, &err_addr, (uint64_t)count);
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else
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amdgpu_ras_error_statistic_ce_count(err_data,
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&mcm_info, &err_addr, (uint64_t)count);
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}
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out_mca_release:
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amdgpu_mca_bank_set_release(&mca_set);
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return ret;
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}
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int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
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{
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const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
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if (!count)
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return -EINVAL;
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if (mca_funcs && mca_funcs->mca_get_valid_mca_count)
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return mca_funcs->mca_get_valid_mca_count(adev, type, count);
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return -EOPNOTSUPP;
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}
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int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
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enum amdgpu_mca_error_type type, uint32_t *total)
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{
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const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
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struct mca_bank_set mca_set;
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struct mca_bank_node *node;
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struct mca_bank_entry *entry;
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uint32_t count;
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int ret;
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if (!total)
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return -EINVAL;
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if (!mca_funcs)
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return -EOPNOTSUPP;
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if (!mca_funcs->mca_get_ras_mca_set || !mca_funcs->mca_get_valid_mca_count)
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return -EOPNOTSUPP;
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amdgpu_mca_bank_set_init(&mca_set);
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ret = mca_funcs->mca_get_ras_mca_set(adev, blk, type, &mca_set);
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if (ret)
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goto err_mca_set_release;
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*total = 0;
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list_for_each_entry(node, &mca_set.list, node) {
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entry = &node->entry;
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count = 0;
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ret = mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, &count);
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if (ret)
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goto err_mca_set_release;
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*total += count;
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}
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err_mca_set_release:
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amdgpu_mca_bank_set_release(&mca_set);
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return ret;
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}
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int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
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{
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const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
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if (!count || !entry)
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return -EINVAL;
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if (!mca_funcs || !mca_funcs->mca_parse_mca_error_count)
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return -EOPNOTSUPP;
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return mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, count);
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}
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int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
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enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set)
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{
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const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
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if (!mca_set)
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return -EINVAL;
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if (!mca_funcs || !mca_funcs->mca_get_ras_mca_set)
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return -EOPNOTSUPP;
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WARN_ON(!list_empty(&mca_set->list));
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return mca_funcs->mca_get_ras_mca_set(adev, blk, type, mca_set);
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}
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int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
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int idx, struct mca_bank_entry *entry)
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{
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const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
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int count;
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if (!mca_funcs || !mca_funcs->mca_get_mca_entry)
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return -EOPNOTSUPP;
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switch (type) {
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case AMDGPU_MCA_ERROR_TYPE_UE:
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count = mca_funcs->max_ue_count;
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break;
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case AMDGPU_MCA_ERROR_TYPE_CE:
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count = mca_funcs->max_ce_count;
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break;
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default:
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return -EINVAL;
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}
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if (idx >= count)
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return -EINVAL;
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return mca_funcs->mca_get_mca_entry(adev, type, idx, entry);
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}
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#if defined(CONFIG_DEBUG_FS)
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static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)data;
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int ret;
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ret = amdgpu_ras_set_mca_debug_mode(adev, val ? true : false);
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if (ret)
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return ret;
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dev_info(adev->dev, "amdgpu set smu mca debug mode %s success\n", val ? "on" : "off");
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return 0;
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}
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static void mca_dump_entry(struct seq_file *m, struct mca_bank_entry *entry)
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{
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int i, idx = entry->idx;
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int reg_idx_array[] = {
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MCA_REG_IDX_STATUS,
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MCA_REG_IDX_ADDR,
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MCA_REG_IDX_MISC0,
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MCA_REG_IDX_IPID,
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MCA_REG_IDX_SYND,
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};
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seq_printf(m, "mca entry[%d].type: %s\n", idx, entry->type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE");
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seq_printf(m, "mca entry[%d].ip: %d\n", idx, entry->ip);
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seq_printf(m, "mca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n",
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idx, entry->info.socket_id, entry->info.aid, entry->info.hwid, entry->info.mcatype);
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for (i = 0; i < ARRAY_SIZE(reg_idx_array); i++)
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seq_printf(m, "mca entry[%d].regs[%d]: 0x%016llx\n", idx, reg_idx_array[i], entry->regs[reg_idx_array[i]]);
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}
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static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
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struct mca_bank_entry *entry;
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uint32_t count = 0;
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int i, ret;
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ret = amdgpu_mca_smu_get_valid_mca_count(adev, type, &count);
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if (ret)
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return ret;
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seq_printf(m, "amdgpu smu %s valid mca count: %d\n",
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type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", count);
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if (!count)
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return 0;
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entry = kmalloc(sizeof(*entry), GFP_KERNEL);
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if (!entry)
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return -ENOMEM;
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for (i = 0; i < count; i++) {
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memset(entry, 0, sizeof(*entry));
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ret = amdgpu_mca_smu_get_mca_entry(adev, type, i, entry);
|
|
if (ret)
|
|
goto err_free_entry;
|
|
|
|
mca_dump_entry(m, entry);
|
|
}
|
|
|
|
err_free_entry:
|
|
kfree(entry);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mca_dump_ce_show(struct seq_file *m, void *unused)
|
|
{
|
|
return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_CE);
|
|
}
|
|
|
|
static int mca_dump_ce_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, mca_dump_ce_show, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations mca_ce_dump_debug_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = mca_dump_ce_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
static int mca_dump_ue_show(struct seq_file *m, void *unused)
|
|
{
|
|
return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_UE);
|
|
}
|
|
|
|
static int mca_dump_ue_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, mca_dump_ue_show, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations mca_ue_dump_debug_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = mca_dump_ue_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n");
|
|
#endif
|
|
|
|
void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
if (!root || amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6))
|
|
return;
|
|
|
|
debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops);
|
|
debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops);
|
|
debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops);
|
|
#endif
|
|
}
|
|
|