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92499dec3a
Add NAND support. The sama7g5's SMC IP is the same as sama5d2's with a slightly change: it provides a synchronous clock output (SMC clock) that is dedicated to FPGA usage. Since this doesn't interfere with the SMC NAND configuration, thus code will not be added in the current nand driver to address the FPGA usage, use the sama5d2's compatible and choose not to introduce dedicated compatibles for sama7g5. Tested with Micron MT29F4G08ABAEAWP NAND flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> [nicolas.ferre@microchip.com: add the definition of PMC_MCK1 in include/dt-bindings/clock/at91.h from another patch] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220111130556.905978-1-tudor.ambarus@microchip.com
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This header provides constants for AT91 pmc status.
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*
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* The constants defined in this header are being used in dts.
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*/
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#ifndef _DT_BINDINGS_CLK_AT91_H
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#define _DT_BINDINGS_CLK_AT91_H
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#define PMC_TYPE_CORE 0
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#define PMC_TYPE_SYSTEM 1
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#define PMC_TYPE_PERIPHERAL 2
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#define PMC_TYPE_GCK 3
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#define PMC_TYPE_PROGRAMMABLE 4
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#define PMC_SLOW 0
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#define PMC_MCK 1
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#define PMC_UTMI 2
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#define PMC_MAIN 3
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#define PMC_MCK2 4
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#define PMC_I2S0_MUX 5
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#define PMC_I2S1_MUX 6
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#define PMC_PLLACK 7
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#define PMC_PLLBCK 8
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#define PMC_AUDIOPLLCK 9
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#define PMC_AUDIOPINCK 10
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/* SAMA7G5 */
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#define PMC_CPUPLL (PMC_MAIN + 1)
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#define PMC_SYSPLL (PMC_MAIN + 2)
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#define PMC_DDRPLL (PMC_MAIN + 3)
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#define PMC_IMGPLL (PMC_MAIN + 4)
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#define PMC_BAUDPLL (PMC_MAIN + 5)
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#define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
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#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
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#define PMC_ETHPLL (PMC_MAIN + 8)
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#define PMC_CPU (PMC_MAIN + 9)
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#define PMC_MCK1 (PMC_MAIN + 10)
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#ifndef AT91_PMC_MOSCS
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#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
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#define AT91_PMC_LOCKA 1 /* PLLA Lock */
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#define AT91_PMC_LOCKB 2 /* PLLB Lock */
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#define AT91_PMC_MCKRDY 3 /* Master Clock */
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#define AT91_PMC_LOCKU 6 /* UPLL Lock */
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#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
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#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
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#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
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#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
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#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
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#endif
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#endif
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