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The Ingenic JZ4760 and JZ4770 both have an extra DMA core named BDMA dedicated to the NAND and BCH controller, but which can also do memory-to-memory transfers. The JZ4760 additionally has a DMA core named MDMA dedicated to memory-to-memory transfers. The programming manual for the JZ4770 does have a bit for a MDMA clock, but does not seem to have the hardware wired in. Add macros for the MDMA and BDMA clocks to the dt-bindings include files, so that they can be used within Device Tree files. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211220193319.114974-2-paul@crapouillou.net Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides clock numbers for the ingenic,jz4760-cgu DT binding.
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*/
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#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
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#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
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#define JZ4760_CLK_EXT 0
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#define JZ4760_CLK_OSC32K 1
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#define JZ4760_CLK_PLL0 2
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#define JZ4760_CLK_PLL0_HALF 3
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#define JZ4760_CLK_PLL1 4
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#define JZ4760_CLK_CCLK 5
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#define JZ4760_CLK_HCLK 6
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#define JZ4760_CLK_SCLK 7
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#define JZ4760_CLK_H2CLK 8
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#define JZ4760_CLK_MCLK 9
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#define JZ4760_CLK_PCLK 10
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#define JZ4760_CLK_MMC_MUX 11
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#define JZ4760_CLK_MMC0 12
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#define JZ4760_CLK_MMC1 13
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#define JZ4760_CLK_MMC2 14
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#define JZ4760_CLK_CIM 15
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#define JZ4760_CLK_UHC 16
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#define JZ4760_CLK_GPU 17
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#define JZ4760_CLK_GPS 18
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#define JZ4760_CLK_SSI_MUX 19
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#define JZ4760_CLK_PCM 20
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#define JZ4760_CLK_I2S 21
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#define JZ4760_CLK_OTG 22
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#define JZ4760_CLK_SSI0 23
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#define JZ4760_CLK_SSI1 24
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#define JZ4760_CLK_SSI2 25
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#define JZ4760_CLK_DMA 26
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#define JZ4760_CLK_I2C0 27
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#define JZ4760_CLK_I2C1 28
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#define JZ4760_CLK_UART0 29
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#define JZ4760_CLK_UART1 30
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#define JZ4760_CLK_UART2 31
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#define JZ4760_CLK_UART3 32
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#define JZ4760_CLK_IPU 33
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#define JZ4760_CLK_ADC 34
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#define JZ4760_CLK_AIC 35
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#define JZ4760_CLK_VPU 36
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#define JZ4760_CLK_UHC_PHY 37
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#define JZ4760_CLK_OTG_PHY 38
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#define JZ4760_CLK_EXT512 39
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#define JZ4760_CLK_RTC 40
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#define JZ4760_CLK_LPCLK_DIV 41
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#define JZ4760_CLK_TVE 42
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#define JZ4760_CLK_LPCLK 43
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#define JZ4760_CLK_MDMA 44
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#define JZ4760_CLK_BDMA 45
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#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */
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