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4299f85a67
The Sparx5 support 9 different clock outputs. This include file has defines for each supported clock ordinal. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200727084211.6632-8-lars.povlsen@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
23 lines
440 B
C
23 lines
440 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019 Microchip Inc.
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*
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* Author: Lars Povlsen <lars.povlsen@microchip.com>
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*/
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#ifndef _DT_BINDINGS_CLK_SPARX5_H
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#define _DT_BINDINGS_CLK_SPARX5_H
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#define CLK_ID_CORE 0
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#define CLK_ID_DDR 1
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#define CLK_ID_CPU2 2
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#define CLK_ID_ARM2 3
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#define CLK_ID_AUX1 4
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#define CLK_ID_AUX2 5
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#define CLK_ID_AUX3 6
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#define CLK_ID_AUX4 7
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#define CLK_ID_SYNCE 8
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#define N_CLOCKS 9
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#endif
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