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Add device tree bindings for display clock controller subsystem for Qualcomm Technology Inc's SC7280 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1626189143-12957-3-git-send-email-tdas@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
55 lines
1.9 KiB
C
55 lines
1.9 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_DP_AUX_CLK 7
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
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#define DISP_CC_MDSS_DP_CRYPTO_CLK 9
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#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
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#define DISP_CC_MDSS_DP_LINK_CLK 11
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
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#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
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#define DISP_CC_MDSS_DP_PIXEL_CLK 15
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
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#define DISP_CC_MDSS_EDP_AUX_CLK 17
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#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 18
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#define DISP_CC_MDSS_EDP_LINK_CLK 19
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#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 20
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#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 21
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#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 22
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#define DISP_CC_MDSS_EDP_PIXEL_CLK 23
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#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 24
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#define DISP_CC_MDSS_ESC0_CLK 25
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#define DISP_CC_MDSS_ESC0_CLK_SRC 26
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#define DISP_CC_MDSS_MDP_CLK 27
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#define DISP_CC_MDSS_MDP_CLK_SRC 28
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#define DISP_CC_MDSS_MDP_LUT_CLK 29
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30
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#define DISP_CC_MDSS_PCLK0_CLK 31
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 32
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#define DISP_CC_MDSS_ROT_CLK 33
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#define DISP_CC_MDSS_ROT_CLK_SRC 34
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#define DISP_CC_MDSS_RSCC_AHB_CLK 35
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 36
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#define DISP_CC_MDSS_VSYNC_CLK 37
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 38
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#define DISP_CC_SLEEP_CLK 39
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#define DISP_CC_XO_CLK 40
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#endif
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