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8397c9c0c2
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6125 SoC. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-3-marijn.suijten@somainline.org
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
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#define DISP_CC_MDSS_DP_AUX_CLK 6
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7
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#define DISP_CC_MDSS_DP_CRYPTO_CLK 8
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#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9
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#define DISP_CC_MDSS_DP_LINK_CLK 10
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 12
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#define DISP_CC_MDSS_DP_PIXEL_CLK 13
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 14
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#define DISP_CC_MDSS_ESC0_CLK 15
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#define DISP_CC_MDSS_ESC0_CLK_SRC 16
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#define DISP_CC_MDSS_MDP_CLK 17
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#define DISP_CC_MDSS_MDP_CLK_SRC 18
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#define DISP_CC_MDSS_MDP_LUT_CLK 19
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 20
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#define DISP_CC_MDSS_PCLK0_CLK 21
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 22
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#define DISP_CC_MDSS_ROT_CLK 23
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#define DISP_CC_MDSS_ROT_CLK_SRC 24
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#define DISP_CC_MDSS_VSYNC_CLK 25
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 26
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#define DISP_CC_XO_CLK 27
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#endif
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