173 lines
6.3 KiB
Plaintext
173 lines
6.3 KiB
Plaintext
What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
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Date: January 2023
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KernelVersion 6.2
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Run integration test for tpdm. Integration test
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will generate test data for tpdm. It can help to make
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sure that the trace path is enabled and the link configurations
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are fine.
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Accepts only one of the 2 values - 1 or 2.
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1 : Generate 64 bits data
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2 : Generate 32 bits data
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What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Reset the dataset of the tpdm.
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Accepts only one value - 1.
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1 : Reset the dataset of the tpdm
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the trigger type of the DSB for tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB trigger type to false
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1 : Set the DSB trigger type to true
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the trigger timestamp of the DSB for tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB trigger type to false
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1 : Set the DSB trigger type to true
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the programming mode of the DSB for tpdm.
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Accepts the value needs to be greater than 0. What data
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bits do is listed below.
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Bit[0:1] : Test mode control bit for choosing the inputs.
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Bit[3] : Set to 0 for low performance mode. Set to 1 for high
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performance mode.
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Bit[4:8] : Select byte lane for high performance mode.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the index number of the edge detection for the DSB
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subunit TPDM. Since there are at most 256 edge detections, this
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value ranges from 0 to 255.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Write a data to control the edge detection corresponding to
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the index number. Before writing data to this sysfs file,
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"ctrl_idx" should be written first to configure the index
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number of the edge detection which needs to be controlled.
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Accepts only one of the following values.
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0 - Rising edge detection
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1 - Falling edge detection
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2 - Rising and falling edge detection (toggle detection)
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Write a data to mask the edge detection corresponding to the index
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number. Before writing data to this sysfs file, "ctrl_idx" should
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be written first to configure the index number of the edge detection
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which needs to be masked.
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Accepts only one of the 2 values - 0 or 1.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Read a set of the edge control value of the DSB in TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Read a set of the edge control mask of the DSB in TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the trigger pattern for the DSB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the mask of the trigger pattern for the DSB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Set the pattern timestamp of DSB tpdm. Read
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the pattern timestamp of DSB tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Disable DSB pattern timestamp.
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1 : Enable DSB pattern timestamp.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Set the pattern type of DSB tpdm. Read
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the pattern type of DSB tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB pattern type to value.
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1 : Set the DSB pattern type to toggle.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the MSR(mux select register) for the DSB subunit
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TPDM.
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