224 lines
6.5 KiB
C
224 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _CORESIGHT_CORESIGHT_TPDM_H
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#define _CORESIGHT_CORESIGHT_TPDM_H
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/* The max number of the datasets that TPDM supports */
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#define TPDM_DATASETS 7
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/* DSB Subunit Registers */
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#define TPDM_DSB_CR (0x780)
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#define TPDM_DSB_TIER (0x784)
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#define TPDM_DSB_TPR(n) (0x788 + (n * 4))
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#define TPDM_DSB_TPMR(n) (0x7A8 + (n * 4))
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#define TPDM_DSB_XPR(n) (0x7C8 + (n * 4))
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#define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4))
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#define TPDM_DSB_EDCR(n) (0x808 + (n * 4))
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#define TPDM_DSB_EDCMR(n) (0x848 + (n * 4))
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#define TPDM_DSB_MSR(n) (0x980 + (n * 4))
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/* Enable bit for DSB subunit */
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#define TPDM_DSB_CR_ENA BIT(0)
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/* Enable bit for DSB subunit perfmance mode */
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#define TPDM_DSB_CR_MODE BIT(1)
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/* Enable bit for DSB subunit trigger type */
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#define TPDM_DSB_CR_TRIG_TYPE BIT(12)
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/* Data bits for DSB high performace mode */
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#define TPDM_DSB_CR_HPSEL GENMASK(6, 2)
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/* Data bits for DSB test mode */
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#define TPDM_DSB_CR_TEST_MODE GENMASK(10, 9)
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/* Enable bit for DSB subunit pattern timestamp */
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#define TPDM_DSB_TIER_PATT_TSENAB BIT(0)
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/* Enable bit for DSB subunit trigger timestamp */
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#define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1)
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/* Bit for DSB subunit pattern type */
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#define TPDM_DSB_TIER_PATT_TYPE BIT(2)
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/* DSB programming modes */
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/* DSB mode bits mask */
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#define TPDM_DSB_MODE_MASK GENMASK(8, 0)
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/* Test mode control bit*/
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#define TPDM_DSB_MODE_TEST(val) (val & GENMASK(1, 0))
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/* Performance mode */
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#define TPDM_DSB_MODE_PERF BIT(3)
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/* High performance mode */
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#define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4))
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#define EDCRS_PER_WORD 16
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#define EDCR_TO_WORD_IDX(r) ((r) / EDCRS_PER_WORD)
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#define EDCR_TO_WORD_SHIFT(r) ((r % EDCRS_PER_WORD) * 2)
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#define EDCR_TO_WORD_VAL(val, r) (val << EDCR_TO_WORD_SHIFT(r))
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#define EDCR_TO_WORD_MASK(r) EDCR_TO_WORD_VAL(0x3, r)
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#define EDCMRS_PER_WORD 32
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#define EDCMR_TO_WORD_IDX(r) ((r) / EDCMRS_PER_WORD)
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#define EDCMR_TO_WORD_SHIFT(r) ((r) % EDCMRS_PER_WORD)
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/* TPDM integration test registers */
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#define TPDM_ITATBCNTRL (0xEF0)
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#define TPDM_ITCNTRL (0xF00)
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/* Register value for integration test */
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#define ATBCNTRL_VAL_32 0xC00F1409
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#define ATBCNTRL_VAL_64 0xC01F1409
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/*
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* Number of cycles to write value when
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* integration test.
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*/
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#define INTEGRATION_TEST_CYCLE 10
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/**
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* The bits of PERIPHIDR0 register.
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* The fields [6:0] of PERIPHIDR0 are used to determine what
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* interfaces and subunits are present on a given TPDM.
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*
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* PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
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* PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
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*/
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#define TPDM_PIDR0_DS_IMPDEF BIT(0)
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#define TPDM_PIDR0_DS_DSB BIT(1)
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#define TPDM_DSB_MAX_LINES 256
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/* MAX number of EDCR registers */
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#define TPDM_DSB_MAX_EDCR 16
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/* MAX number of EDCMR registers */
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#define TPDM_DSB_MAX_EDCMR 8
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/* MAX number of DSB pattern */
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#define TPDM_DSB_MAX_PATT 8
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/* MAX number of DSB MSR */
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#define TPDM_DSB_MAX_MSR 32
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#define tpdm_simple_dataset_ro(name, mem, idx) \
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(&((struct tpdm_dataset_attribute[]) { \
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{ \
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__ATTR(name, 0444, tpdm_simple_dataset_show, NULL), \
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mem, \
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idx, \
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} \
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})[0].attr.attr)
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#define tpdm_simple_dataset_rw(name, mem, idx) \
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(&((struct tpdm_dataset_attribute[]) { \
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{ \
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__ATTR(name, 0644, tpdm_simple_dataset_show, \
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tpdm_simple_dataset_store), \
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mem, \
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idx, \
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} \
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})[0].attr.attr)
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#define DSB_EDGE_CTRL_ATTR(nr) \
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tpdm_simple_dataset_ro(edcr##nr, \
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DSB_EDGE_CTRL, nr)
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#define DSB_EDGE_CTRL_MASK_ATTR(nr) \
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tpdm_simple_dataset_ro(edcmr##nr, \
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DSB_EDGE_CTRL_MASK, nr)
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#define DSB_TRIG_PATT_ATTR(nr) \
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tpdm_simple_dataset_rw(xpr##nr, \
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DSB_TRIG_PATT, nr)
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#define DSB_TRIG_PATT_MASK_ATTR(nr) \
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tpdm_simple_dataset_rw(xpmr##nr, \
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DSB_TRIG_PATT_MASK, nr)
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#define DSB_PATT_ATTR(nr) \
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tpdm_simple_dataset_rw(tpr##nr, \
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DSB_PATT, nr)
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#define DSB_PATT_MASK_ATTR(nr) \
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tpdm_simple_dataset_rw(tpmr##nr, \
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DSB_PATT_MASK, nr)
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#define DSB_MSR_ATTR(nr) \
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tpdm_simple_dataset_rw(msr##nr, \
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DSB_MSR, nr)
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/**
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* struct dsb_dataset - specifics associated to dsb dataset
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* @mode: DSB programming mode
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* @edge_ctrl_idx Index number of the edge control
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* @edge_ctrl: Save value for edge control
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* @edge_ctrl_mask: Save value for edge control mask
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* @patt_val: Save value for pattern
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* @patt_mask: Save value for pattern mask
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* @trig_patt: Save value for trigger pattern
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* @trig_patt_mask: Save value for trigger pattern mask
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* @msr Save value for MSR
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* @patt_ts: Enable/Disable pattern timestamp
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* @patt_type: Set pattern type
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* @trig_ts: Enable/Disable trigger timestamp.
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* @trig_type: Enable/Disable trigger type.
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*/
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struct dsb_dataset {
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u32 mode;
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u32 edge_ctrl_idx;
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u32 edge_ctrl[TPDM_DSB_MAX_EDCR];
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u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR];
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u32 patt_val[TPDM_DSB_MAX_PATT];
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u32 patt_mask[TPDM_DSB_MAX_PATT];
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u32 trig_patt[TPDM_DSB_MAX_PATT];
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u32 trig_patt_mask[TPDM_DSB_MAX_PATT];
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u32 msr[TPDM_DSB_MAX_MSR];
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bool patt_ts;
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bool patt_type;
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bool trig_ts;
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bool trig_type;
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};
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/**
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* struct tpdm_drvdata - specifics associated to an TPDM component
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* @base: memory mapped base address for this component.
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* @dev: The device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @spinlock: lock for the drvdata value.
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* @enable: enable status of the component.
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* @datasets: The datasets types present of the TPDM.
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* @dsb Specifics associated to TPDM DSB.
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* @dsb_msr_num Number of MSR supported by DSB TPDM
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*/
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struct tpdm_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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spinlock_t spinlock;
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bool enable;
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unsigned long datasets;
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struct dsb_dataset *dsb;
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u32 dsb_msr_num;
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};
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/* Enumerate members of various datasets */
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enum dataset_mem {
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DSB_EDGE_CTRL,
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DSB_EDGE_CTRL_MASK,
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DSB_TRIG_PATT,
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DSB_TRIG_PATT_MASK,
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DSB_PATT,
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DSB_PATT_MASK,
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DSB_MSR,
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};
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/**
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* struct tpdm_dataset_attribute - Record the member variables and
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* index number of datasets that need to be operated by sysfs file
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* @attr: The device attribute
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* @mem: The member in the dataset data structure
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* @idx: The index number of the array data
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*/
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struct tpdm_dataset_attribute {
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struct device_attribute attr;
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enum dataset_mem mem;
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u32 idx;
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};
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#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
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