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e6e6600c00
ccree had a mechanism for IV generation which was not compatible with the Linux seqiv or echainiv iv generator and was never used in any of the upstream versions so drop all the code implementing it. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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/* \file cc_aead.h
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* ARM CryptoCell AEAD Crypto API
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*/
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#ifndef __CC_AEAD_H__
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#define __CC_AEAD_H__
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#include <linux/kernel.h>
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#include <crypto/algapi.h>
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#include <crypto/ctr.h>
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/* mac_cmp - HW writes 8 B but all bytes hold the same value */
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#define ICV_CMP_SIZE 8
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#define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3)
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#define MAX_MAC_SIZE SHA256_DIGEST_SIZE
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/* defines for AES GCM configuration buffer */
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#define GCM_BLOCK_LEN_SIZE 8
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#define GCM_BLOCK_RFC4_IV_OFFSET 4
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#define GCM_BLOCK_RFC4_IV_SIZE 8 /* IV size for rfc's */
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#define GCM_BLOCK_RFC4_NONCE_OFFSET 0
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#define GCM_BLOCK_RFC4_NONCE_SIZE 4
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/* Offsets into AES CCM configuration buffer */
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#define CCM_B0_OFFSET 0
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#define CCM_A0_OFFSET 16
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#define CCM_CTR_COUNT_0_OFFSET 32
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/* CCM B0 and CTR_COUNT constants. */
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#define CCM_BLOCK_NONCE_OFFSET 1 /* Nonce offset inside B0 and CTR_COUNT */
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#define CCM_BLOCK_NONCE_SIZE 3 /* Nonce size inside B0 and CTR_COUNT */
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#define CCM_BLOCK_IV_OFFSET 4 /* IV offset inside B0 and CTR_COUNT */
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#define CCM_BLOCK_IV_SIZE 8 /* IV size inside B0 and CTR_COUNT */
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enum aead_ccm_header_size {
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ccm_header_size_null = -1,
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ccm_header_size_zero = 0,
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ccm_header_size_2 = 2,
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ccm_header_size_6 = 6,
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ccm_header_size_max = S32_MAX
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};
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struct aead_req_ctx {
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/* Allocate cache line although only 4 bytes are needed to
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* assure next field falls @ cache line
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* Used for both: digest HW compare and CCM/GCM MAC value
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*/
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u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
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u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
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//used in gcm
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u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
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u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
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u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
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struct {
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u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
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u8 len_c[GCM_BLOCK_LEN_SIZE];
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} gcm_len_block;
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u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
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/* HW actual size input */
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unsigned int hw_iv_size ____cacheline_aligned;
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/* used to prevent cache coherence problem */
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u8 backup_mac[MAX_MAC_SIZE];
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u8 *backup_iv; /* store orig iv */
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u32 assoclen; /* internal assoclen */
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dma_addr_t mac_buf_dma_addr; /* internal ICV DMA buffer */
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/* buffer for internal ccm configurations */
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dma_addr_t ccm_iv0_dma_addr;
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dma_addr_t icv_dma_addr; /* Phys. address of ICV */
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//used in gcm
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/* buffer for internal gcm configurations */
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dma_addr_t gcm_iv_inc1_dma_addr;
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/* buffer for internal gcm configurations */
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dma_addr_t gcm_iv_inc2_dma_addr;
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dma_addr_t hkey_dma_addr; /* Phys. address of hkey */
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dma_addr_t gcm_block_len_dma_addr; /* Phys. address of gcm block len */
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bool is_gcm4543;
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u8 *icv_virt_addr; /* Virt. address of ICV */
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struct async_gen_req_ctx gen_ctx;
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struct cc_mlli assoc;
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struct cc_mlli src;
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struct cc_mlli dst;
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struct scatterlist *src_sgl;
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struct scatterlist *dst_sgl;
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unsigned int src_offset;
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unsigned int dst_offset;
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enum cc_req_dma_buf_type assoc_buff_type;
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enum cc_req_dma_buf_type data_buff_type;
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struct mlli_params mlli_params;
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unsigned int cryptlen;
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struct scatterlist ccm_adata_sg;
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enum aead_ccm_header_size ccm_hdr_size;
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unsigned int req_authsize;
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enum drv_cipher_mode cipher_mode;
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bool is_icv_fragmented;
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bool is_single_pass;
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bool plaintext_authenticate_only; //for gcm_rfc4543
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};
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int cc_aead_alloc(struct cc_drvdata *drvdata);
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int cc_aead_free(struct cc_drvdata *drvdata);
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#endif /*__CC_AEAD_H__*/
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