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62c455ca85
The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It uses Hisilicon QM as the interface to the CPU. This patch provides PCIe driver to the accelerator and registers it to crypto acomp interface. It also uses sgl as data input/output interface. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Kenneth Lee <liguozhu@hisilicon.com> Signed-off-by: Hao Fang <fanghao11@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
5 lines
199 B
Makefile
5 lines
199 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CRYPTO_DEV_HISI_SEC) += sec/
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obj-$(CONFIG_CRYPTO_DEV_HISI_QM) += qm.o
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obj-$(CONFIG_CRYPTO_HISI_SGL) += sgl.o
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obj-$(CONFIG_CRYPTO_DEV_HISI_ZIP) += zip/
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