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090ab3ff8e
This allows a ROM-able zImage to be written to eSD and for SuperH Mobile ARM to boot directly from the SDHI hardware block. This is achieved by the MaskROM loading the first portion of the image into MERAM and then jumping to it. This portion contains loader code which copies the entire image to SDRAM and jumps to it. From there the zImage boot code proceeds as normal, uncompressing the image into its final location and then jumping to it. Cc: Paul Mundt <lethal@linux-sh.org> Acked-by: Magnus Damm <magnus.damm@gmail.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* sh7372 MMCIF loader
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 Simon Horman
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mmc/sh_mmcif.h>
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#include <linux/mmc/boot.h>
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#include <mach/mmc.h>
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#define MMCIF_BASE (void __iomem *)0xe6bd0000
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#define PORT84CR (void __iomem *)0xe6050054
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#define PORT85CR (void __iomem *)0xe6050055
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#define PORT86CR (void __iomem *)0xe6050056
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#define PORT87CR (void __iomem *)0xe6050057
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#define PORT88CR (void __iomem *)0xe6050058
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#define PORT89CR (void __iomem *)0xe6050059
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#define PORT90CR (void __iomem *)0xe605005a
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#define PORT91CR (void __iomem *)0xe605005b
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#define PORT92CR (void __iomem *)0xe605005c
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#define PORT99CR (void __iomem *)0xe6050063
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#define SMSTPCR3 (void __iomem *)0xe615013c
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/* SH7372 specific MMCIF loader
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*
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* loads the zImage from an MMC card starting from block 1.
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*
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* The image must be start with a vrl4 header and
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* the zImage must start at offset 512 of the image. That is,
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* at block 2 (=byte 1024) on the media
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*
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* Use the following line to write the vrl4 formated zImage
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* to an MMC card
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* # dd if=vrl4.out of=/dev/sdx bs=512 seek=1
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*/
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asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
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{
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mmc_init_progress();
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mmc_update_progress(MMC_PROGRESS_ENTER);
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/* Initialise MMC
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* registers: PORT84CR-PORT92CR
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* (MMCD0_0-MMCD0_7,MMCCMD0 Control)
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* value: 0x04 - select function 4
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*/
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__raw_writeb(0x04, PORT84CR);
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__raw_writeb(0x04, PORT85CR);
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__raw_writeb(0x04, PORT86CR);
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__raw_writeb(0x04, PORT87CR);
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__raw_writeb(0x04, PORT88CR);
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__raw_writeb(0x04, PORT89CR);
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__raw_writeb(0x04, PORT90CR);
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__raw_writeb(0x04, PORT91CR);
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__raw_writeb(0x04, PORT92CR);
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/* Initialise MMC
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* registers: PORT99CR (MMCCLK0 Control)
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* value: 0x10 | 0x04 - enable output | select function 4
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*/
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__raw_writeb(0x14, PORT99CR);
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/* Enable clock to MMC hardware block */
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__raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3);
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mmc_update_progress(MMC_PROGRESS_INIT);
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/* setup MMCIF hardware */
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sh_mmcif_boot_init(MMCIF_BASE);
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mmc_update_progress(MMC_PROGRESS_LOAD);
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/* load kernel via MMCIF interface */
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sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */
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(len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf);
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/* Disable clock to MMC hardware block */
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__raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3);
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mmc_update_progress(MMC_PROGRESS_DONE);
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}
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