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707abf0695
The LTR message on the PCIe inform the requested latency on which the PCIe must become active to the downstream PCIe port of the system. This patch provide recommended LTR parameters by i225 specification. Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
16 lines
501 B
C
16 lines
501 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018 Intel Corporation */
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#ifndef _IGC_I225_H_
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#define _IGC_I225_H_
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s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask);
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void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask);
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s32 igc_init_nvm_params_i225(struct igc_hw *hw);
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bool igc_get_flash_presence_i225(struct igc_hw *hw);
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s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
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bool adv100M);
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s32 igc_set_ltr_i225(struct igc_hw *hw, bool link);
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#endif
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