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1f62ed00a5
C-SKY MMU would pre-fetch invalid pte entries, and it could work with
flush_tlb_fix_spurious_fault, but the additional page fault exceptions
would reduce performance. So flushing the entry of the TLB would prevent
the following spurious page faults. Here is the test code:
define DATA_LEN 4096
define COPY_NUM (504*100)
unsigned char src[DATA_LEN*COPY_NUM] = {0};
unsigned char dst[DATA_LEN*COPY_NUM] = {0};
unsigned char func_src[DATA_LEN*COPY_NUM] = {0};
unsigned char func_dst[DATA_LEN*COPY_NUM] = {0};
void main(void)
{
int j;
for (j = 0; j < COPY_NUM; j++)
memcpy(&dst[j*DATA_LEN], &src[j*DATA_LEN], 4);
}
perf stat -e page-faults ./main.elf
The amount of page fault traps would be reduced in half with the patch.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
91 lines
2 KiB
C
91 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/cache.h>
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#include <linux/highmem.h>
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#include <linux/mm.h>
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#include <asm/cache.h>
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#include <asm/tlbflush.h>
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *pte)
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{
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unsigned long addr;
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struct page *page;
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flush_tlb_page(vma, address);
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if (!pfn_valid(pte_pfn(*pte)))
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return;
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page = pfn_to_page(pte_pfn(*pte));
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if (page == ZERO_PAGE(0))
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return;
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if (test_and_set_bit(PG_dcache_clean, &page->flags))
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return;
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addr = (unsigned long) kmap_atomic(page);
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dcache_wb_range(addr, addr + PAGE_SIZE);
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if (vma->vm_flags & VM_EXEC)
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icache_inv_range(addr, addr + PAGE_SIZE);
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kunmap_atomic((void *) addr);
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}
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void flush_icache_deferred(struct mm_struct *mm)
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{
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unsigned int cpu = smp_processor_id();
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cpumask_t *mask = &mm->context.icache_stale_mask;
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if (cpumask_test_cpu(cpu, mask)) {
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cpumask_clear_cpu(cpu, mask);
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/*
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* Ensure the remote hart's writes are visible to this hart.
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* This pairs with a barrier in flush_icache_mm.
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*/
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smp_mb();
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local_icache_inv_all(NULL);
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}
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}
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void flush_icache_mm_range(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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#ifdef CONFIG_CPU_HAS_ICACHE_INS
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if (mm == current->mm) {
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icache_inv_range(start, end);
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preempt_enable();
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return;
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}
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#endif
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_icache_inv_all(NULL);
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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if (mm != current->active_mm || !cpumask_empty(&others)) {
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on_each_cpu_mask(&others, local_icache_inv_all, NULL, 1);
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cpumask_clear(mask);
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}
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preempt_enable();
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}
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