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![Bibby Hsieh](/assets/img/avatar_default.png)
GCE hardware stored event information in own internal sysram,
if the initial value in those sysram is not zero value
it will cause a situation that gce can wait the event immediately
after client ask gce to wait event but not really trigger the
corresponding hardware.
In order to make sure that the wait event function is
exactly correct, we need to clear the sysram value in
cmdq initial flow.
Fixes: 623a6143a8
("mailbox: mediatek: Add Mediatek CMDQ driver")
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
574 lines
15 KiB
C
574 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2018 MediaTek Inc.
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mailbox_controller.h>
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#include <linux/mailbox/mtk-cmdq-mailbox.h>
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#include <linux/of_device.h>
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#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
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#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
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#define CMDQ_CURR_IRQ_STATUS 0x10
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#define CMDQ_SYNC_TOKEN_UPDATE 0x68
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#define CMDQ_THR_SLOT_CYCLES 0x30
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#define CMDQ_THR_BASE 0x100
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#define CMDQ_THR_SIZE 0x80
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#define CMDQ_THR_WARM_RESET 0x00
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#define CMDQ_THR_ENABLE_TASK 0x04
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#define CMDQ_THR_SUSPEND_TASK 0x08
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#define CMDQ_THR_CURR_STATUS 0x0c
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#define CMDQ_THR_IRQ_STATUS 0x10
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#define CMDQ_THR_IRQ_ENABLE 0x14
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#define CMDQ_THR_CURR_ADDR 0x20
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#define CMDQ_THR_END_ADDR 0x24
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#define CMDQ_THR_WAIT_TOKEN 0x30
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#define CMDQ_THR_PRIORITY 0x40
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#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
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#define CMDQ_THR_ENABLED 0x1
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#define CMDQ_THR_DISABLED 0x0
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#define CMDQ_THR_SUSPEND 0x1
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#define CMDQ_THR_RESUME 0x0
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#define CMDQ_THR_STATUS_SUSPENDED BIT(1)
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#define CMDQ_THR_DO_WARM_RESET BIT(0)
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#define CMDQ_THR_IRQ_DONE 0x1
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#define CMDQ_THR_IRQ_ERROR 0x12
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#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
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#define CMDQ_THR_IS_WAITING BIT(31)
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#define CMDQ_JUMP_BY_OFFSET 0x10000000
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#define CMDQ_JUMP_BY_PA 0x10000001
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struct cmdq_thread {
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struct mbox_chan *chan;
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void __iomem *base;
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struct list_head task_busy_list;
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u32 priority;
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bool atomic_exec;
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};
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struct cmdq_task {
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struct cmdq *cmdq;
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struct list_head list_entry;
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dma_addr_t pa_base;
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struct cmdq_thread *thread;
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struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
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};
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struct cmdq {
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struct mbox_controller mbox;
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void __iomem *base;
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u32 irq;
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u32 thread_nr;
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u32 irq_mask;
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struct cmdq_thread *thread;
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struct clk *clock;
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bool suspended;
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};
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static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
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{
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u32 status;
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writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
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/* If already disabled, treat as suspended successful. */
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if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
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return 0;
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if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
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status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
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dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
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(u32)(thread->base - cmdq->base));
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return -EFAULT;
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}
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return 0;
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}
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static void cmdq_thread_resume(struct cmdq_thread *thread)
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{
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writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
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}
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static void cmdq_init(struct cmdq *cmdq)
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{
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int i;
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WARN_ON(clk_enable(cmdq->clock) < 0);
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writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
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for (i = 0; i <= CMDQ_MAX_EVENT; i++)
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writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
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clk_disable(cmdq->clock);
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}
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static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
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{
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u32 warm_reset;
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writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
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if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
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warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
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0, 10)) {
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dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
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(u32)(thread->base - cmdq->base));
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return -EFAULT;
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}
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return 0;
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}
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static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
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{
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cmdq_thread_reset(cmdq, thread);
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writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
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}
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/* notify GCE to re-fetch commands by setting GCE thread PC */
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static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
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{
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writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
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thread->base + CMDQ_THR_CURR_ADDR);
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}
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static void cmdq_task_insert_into_thread(struct cmdq_task *task)
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{
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struct device *dev = task->cmdq->mbox.dev;
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struct cmdq_thread *thread = task->thread;
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struct cmdq_task *prev_task = list_last_entry(
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&thread->task_busy_list, typeof(*task), list_entry);
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u64 *prev_task_base = prev_task->pkt->va_base;
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/* let previous task jump to this task */
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dma_sync_single_for_cpu(dev, prev_task->pa_base,
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prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
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prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
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(u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
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dma_sync_single_for_device(dev, prev_task->pa_base,
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prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
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cmdq_thread_invalidate_fetched_data(thread);
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}
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static bool cmdq_command_is_wfe(u64 cmd)
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{
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u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
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u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
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u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0xffffffff;
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return ((cmd & wfe_mask) == (wfe_op | wfe_option));
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}
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/* we assume tasks in the same display GCE thread are waiting the same event. */
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static void cmdq_task_remove_wfe(struct cmdq_task *task)
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{
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struct device *dev = task->cmdq->mbox.dev;
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u64 *base = task->pkt->va_base;
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int i;
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dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
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DMA_TO_DEVICE);
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for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
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if (cmdq_command_is_wfe(base[i]))
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base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
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CMDQ_JUMP_PASS;
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dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
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DMA_TO_DEVICE);
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}
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static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
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{
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return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
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}
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static void cmdq_thread_wait_end(struct cmdq_thread *thread,
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unsigned long end_pa)
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{
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struct device *dev = thread->chan->mbox->dev;
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unsigned long curr_pa;
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if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
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curr_pa, curr_pa == end_pa, 1, 20))
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dev_err(dev, "GCE thread cannot run to end.\n");
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}
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static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta)
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{
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struct cmdq_task_cb *cb = &task->pkt->async_cb;
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struct cmdq_cb_data data;
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WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL);
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data.sta = sta;
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data.data = cb->data;
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cb->cb(data);
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list_del(&task->list_entry);
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}
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static void cmdq_task_handle_error(struct cmdq_task *task)
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{
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struct cmdq_thread *thread = task->thread;
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struct cmdq_task *next_task;
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dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
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WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
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next_task = list_first_entry_or_null(&thread->task_busy_list,
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struct cmdq_task, list_entry);
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if (next_task)
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writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
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cmdq_thread_resume(thread);
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}
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static void cmdq_thread_irq_handler(struct cmdq *cmdq,
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struct cmdq_thread *thread)
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{
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struct cmdq_task *task, *tmp, *curr_task = NULL;
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u32 curr_pa, irq_flag, task_end_pa;
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bool err;
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irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
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writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
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/*
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* When ISR call this function, another CPU core could run
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* "release task" right before we acquire the spin lock, and thus
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* reset / disable this GCE thread, so we need to check the enable
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* bit of this GCE thread.
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*/
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if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
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return;
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if (irq_flag & CMDQ_THR_IRQ_ERROR)
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err = true;
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else if (irq_flag & CMDQ_THR_IRQ_DONE)
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err = false;
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else
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return;
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curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
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list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
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list_entry) {
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task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
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if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
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curr_task = task;
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if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
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cmdq_task_exec_done(task, CMDQ_CB_NORMAL);
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kfree(task);
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} else if (err) {
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cmdq_task_exec_done(task, CMDQ_CB_ERROR);
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cmdq_task_handle_error(curr_task);
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kfree(task);
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}
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if (curr_task)
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break;
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}
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if (list_empty(&thread->task_busy_list)) {
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cmdq_thread_disable(cmdq, thread);
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clk_disable(cmdq->clock);
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}
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}
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static irqreturn_t cmdq_irq_handler(int irq, void *dev)
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{
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struct cmdq *cmdq = dev;
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unsigned long irq_status, flags = 0L;
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int bit;
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irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
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if (!(irq_status ^ cmdq->irq_mask))
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return IRQ_NONE;
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for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
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struct cmdq_thread *thread = &cmdq->thread[bit];
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spin_lock_irqsave(&thread->chan->lock, flags);
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cmdq_thread_irq_handler(cmdq, thread);
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spin_unlock_irqrestore(&thread->chan->lock, flags);
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}
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return IRQ_HANDLED;
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}
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static int cmdq_suspend(struct device *dev)
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{
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struct cmdq *cmdq = dev_get_drvdata(dev);
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struct cmdq_thread *thread;
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int i;
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bool task_running = false;
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cmdq->suspended = true;
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for (i = 0; i < cmdq->thread_nr; i++) {
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thread = &cmdq->thread[i];
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if (!list_empty(&thread->task_busy_list)) {
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task_running = true;
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break;
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}
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}
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if (task_running)
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dev_warn(dev, "exist running task(s) in suspend\n");
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clk_unprepare(cmdq->clock);
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return 0;
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}
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static int cmdq_resume(struct device *dev)
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{
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struct cmdq *cmdq = dev_get_drvdata(dev);
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WARN_ON(clk_prepare(cmdq->clock) < 0);
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cmdq->suspended = false;
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return 0;
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}
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static int cmdq_remove(struct platform_device *pdev)
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{
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struct cmdq *cmdq = platform_get_drvdata(pdev);
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clk_unprepare(cmdq->clock);
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return 0;
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}
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static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
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struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
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struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
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struct cmdq_task *task;
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unsigned long curr_pa, end_pa;
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/* Client should not flush new tasks if suspended. */
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WARN_ON(cmdq->suspended);
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task = kzalloc(sizeof(*task), GFP_ATOMIC);
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if (!task)
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return -ENOMEM;
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task->cmdq = cmdq;
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INIT_LIST_HEAD(&task->list_entry);
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task->pa_base = pkt->pa_base;
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task->thread = thread;
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task->pkt = pkt;
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if (list_empty(&thread->task_busy_list)) {
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WARN_ON(clk_enable(cmdq->clock) < 0);
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WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
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writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
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writel(task->pa_base + pkt->cmd_buf_size,
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thread->base + CMDQ_THR_END_ADDR);
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writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
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writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
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writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
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} else {
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WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
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curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
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end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
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/*
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* Atomic execution should remove the following wfe, i.e. only
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* wait event at first task, and prevent to pause when running.
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*/
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if (thread->atomic_exec) {
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/* GCE is executing if command is not WFE */
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if (!cmdq_thread_is_in_wfe(thread)) {
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cmdq_thread_resume(thread);
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cmdq_thread_wait_end(thread, end_pa);
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WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
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/* set to this task directly */
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writel(task->pa_base,
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thread->base + CMDQ_THR_CURR_ADDR);
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} else {
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cmdq_task_insert_into_thread(task);
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cmdq_task_remove_wfe(task);
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smp_mb(); /* modify jump before enable thread */
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}
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} else {
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/* check boundary */
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if (curr_pa == end_pa - CMDQ_INST_SIZE ||
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curr_pa == end_pa) {
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/* set to this task directly */
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writel(task->pa_base,
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thread->base + CMDQ_THR_CURR_ADDR);
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} else {
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cmdq_task_insert_into_thread(task);
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smp_mb(); /* modify jump before enable thread */
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}
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}
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writel(task->pa_base + pkt->cmd_buf_size,
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thread->base + CMDQ_THR_END_ADDR);
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cmdq_thread_resume(thread);
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}
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list_move_tail(&task->list_entry, &thread->task_busy_list);
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return 0;
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}
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static int cmdq_mbox_startup(struct mbox_chan *chan)
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{
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return 0;
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}
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static void cmdq_mbox_shutdown(struct mbox_chan *chan)
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{
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}
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static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
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.send_data = cmdq_mbox_send_data,
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.startup = cmdq_mbox_startup,
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.shutdown = cmdq_mbox_shutdown,
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};
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static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *sp)
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{
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int ind = sp->args[0];
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struct cmdq_thread *thread;
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if (ind >= mbox->num_chans)
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return ERR_PTR(-EINVAL);
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thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
|
|
thread->priority = sp->args[1];
|
|
thread->atomic_exec = (sp->args[2] != 0);
|
|
thread->chan = &mbox->chans[ind];
|
|
|
|
return &mbox->chans[ind];
|
|
}
|
|
|
|
static int cmdq_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res;
|
|
struct cmdq *cmdq;
|
|
int err, i;
|
|
|
|
cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
|
|
if (!cmdq)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
cmdq->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(cmdq->base)) {
|
|
dev_err(dev, "failed to ioremap gce\n");
|
|
return PTR_ERR(cmdq->base);
|
|
}
|
|
|
|
cmdq->irq = platform_get_irq(pdev, 0);
|
|
if (!cmdq->irq) {
|
|
dev_err(dev, "failed to get irq\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
|
|
cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
|
|
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
|
|
"mtk_cmdq", cmdq);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to register ISR (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
|
|
dev, cmdq->base, cmdq->irq);
|
|
|
|
cmdq->clock = devm_clk_get(dev, "gce");
|
|
if (IS_ERR(cmdq->clock)) {
|
|
dev_err(dev, "failed to get gce clk\n");
|
|
return PTR_ERR(cmdq->clock);
|
|
}
|
|
|
|
cmdq->mbox.dev = dev;
|
|
cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
|
|
sizeof(*cmdq->mbox.chans), GFP_KERNEL);
|
|
if (!cmdq->mbox.chans)
|
|
return -ENOMEM;
|
|
|
|
cmdq->mbox.num_chans = cmdq->thread_nr;
|
|
cmdq->mbox.ops = &cmdq_mbox_chan_ops;
|
|
cmdq->mbox.of_xlate = cmdq_xlate;
|
|
|
|
/* make use of TXDONE_BY_ACK */
|
|
cmdq->mbox.txdone_irq = false;
|
|
cmdq->mbox.txdone_poll = false;
|
|
|
|
cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
|
|
sizeof(*cmdq->thread), GFP_KERNEL);
|
|
if (!cmdq->thread)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < cmdq->thread_nr; i++) {
|
|
cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
|
|
CMDQ_THR_SIZE * i;
|
|
INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
|
|
cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
|
|
}
|
|
|
|
err = devm_mbox_controller_register(dev, &cmdq->mbox);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to register mailbox: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, cmdq);
|
|
WARN_ON(clk_prepare(cmdq->clock) < 0);
|
|
|
|
cmdq_init(cmdq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops cmdq_pm_ops = {
|
|
.suspend = cmdq_suspend,
|
|
.resume = cmdq_resume,
|
|
};
|
|
|
|
static const struct of_device_id cmdq_of_ids[] = {
|
|
{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
|
|
{.compatible = "mediatek,mt8183-gce", .data = (void *)24},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver cmdq_drv = {
|
|
.probe = cmdq_probe,
|
|
.remove = cmdq_remove,
|
|
.driver = {
|
|
.name = "mtk_cmdq",
|
|
.pm = &cmdq_pm_ops,
|
|
.of_match_table = cmdq_of_ids,
|
|
}
|
|
};
|
|
|
|
static int __init cmdq_drv_init(void)
|
|
{
|
|
return platform_driver_register(&cmdq_drv);
|
|
}
|
|
|
|
static void __exit cmdq_drv_exit(void)
|
|
{
|
|
platform_driver_unregister(&cmdq_drv);
|
|
}
|
|
|
|
subsys_initcall(cmdq_drv_init);
|
|
module_exit(cmdq_drv_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|