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![Krzysztof Kozlowski](/assets/img/avatar_default.png)
Chipsets before Exynos5420 did not support HS400 so if MMC core tries to configure HS400 timing, this might or might not work. Warn in such cases because this is DTB misconfiguration. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
555 lines
15 KiB
C
555 lines
15 KiB
C
/*
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* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2012, Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/mmc/mmc.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#include "dw_mmc-exynos.h"
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/* Variations in Exynos specific dw-mshc controller */
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enum dw_mci_exynos_type {
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4412,
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DW_MCI_TYPE_EXYNOS5250,
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DW_MCI_TYPE_EXYNOS5420,
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DW_MCI_TYPE_EXYNOS5420_SMU,
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DW_MCI_TYPE_EXYNOS7,
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DW_MCI_TYPE_EXYNOS7_SMU,
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};
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/* Exynos implementation specific driver private data */
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struct dw_mci_exynos_priv_data {
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enum dw_mci_exynos_type ctrl_type;
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u8 ciu_div;
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u32 sdr_timing;
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u32 ddr_timing;
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u32 hs400_timing;
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u32 tuned_sample;
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u32 cur_speed;
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u32 dqs_delay;
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u32 saved_dqs_en;
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u32 saved_strobe_ctrl;
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};
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static struct dw_mci_exynos_compatible {
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char *compatible;
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enum dw_mci_exynos_type ctrl_type;
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} exynos_compat[] = {
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{
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.compatible = "samsung,exynos4210-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
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}, {
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.compatible = "samsung,exynos4412-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
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}, {
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.compatible = "samsung,exynos5250-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
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}, {
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.compatible = "samsung,exynos5420-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
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}, {
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.compatible = "samsung,exynos5420-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
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}, {
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.compatible = "samsung,exynos7-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS7,
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}, {
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.compatible = "samsung,exynos7-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
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},
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};
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static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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return EXYNOS4412_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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return EXYNOS4210_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
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else
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return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
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}
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static void dw_mci_exynos_config_smu(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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/*
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* If Exynos is provided the Security management,
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* set for non-ecryption mode at this time.
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*/
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
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mci_writel(host, MPSBEGIN0, 0);
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mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
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mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
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SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
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SDMMC_MPSCTRL_VALID |
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SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
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}
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}
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static int dw_mci_exynos_priv_init(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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dw_mci_exynos_config_smu(host);
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if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
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priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
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priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
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priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
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mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
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if (!priv->dqs_delay)
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priv->dqs_delay =
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DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
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}
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host->bus_hz /= (priv->ciu_div + 1);
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return 0;
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}
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static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 clksel;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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/*
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* Exynos4412 and Exynos5250 extends the use of CMD register with the
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* use of bit 29 (which is reserved on standard MSHC controllers) for
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* optionally bypassing the HOLD register for command and data. The
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* HOLD register should be bypassed in case there is no phase shift
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* applied on CMD/DATA that is sent to the card.
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*/
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if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->cur_slot)
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set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
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}
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#ifdef CONFIG_PM_SLEEP
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static int dw_mci_exynos_suspend(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_suspend(host);
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}
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static int dw_mci_exynos_resume(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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dw_mci_exynos_config_smu(host);
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return dw_mci_resume(host);
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}
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/**
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* dw_mci_exynos_resume_noirq - Exynos-specific resume code
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*
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* On exynos5420 there is a silicon errata that will sometimes leave the
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* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
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* that it fired and we can clear it by writing a 1 back. Clear it to prevent
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* interrupts from going off constantly.
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*
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* We run this code on all exynos variants because it doesn't hurt.
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*/
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static int dw_mci_exynos_resume_noirq(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 clksel;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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}
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return 0;
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}
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#else
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#define dw_mci_exynos_suspend NULL
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#define dw_mci_exynos_resume NULL
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#define dw_mci_exynos_resume_noirq NULL
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#endif /* CONFIG_PM_SLEEP */
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static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 dqs, strobe;
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/*
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* Not supported to configure register
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* related to HS400
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*/
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if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) {
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if (timing == MMC_TIMING_MMC_HS400)
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dev_warn(host->dev,
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"cannot configure HS400, unsupported chipset\n");
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return;
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}
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dqs = priv->saved_dqs_en;
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strobe = priv->saved_strobe_ctrl;
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if (timing == MMC_TIMING_MMC_HS400) {
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dqs |= DATA_STROBE_EN;
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strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
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} else {
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dqs &= ~DATA_STROBE_EN;
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}
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mci_writel(host, HS400_DQS_EN, dqs);
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mci_writel(host, HS400_DLINE_CTRL, strobe);
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}
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static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned long actual;
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u8 div;
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int ret;
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/*
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* Don't care if wanted clock is zero or
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* ciu clock is unavailable
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*/
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if (!wanted || IS_ERR(host->ciu_clk))
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return;
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/* Guaranteed minimum frequency for cclkin */
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if (wanted < EXYNOS_CCLKIN_MIN)
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wanted = EXYNOS_CCLKIN_MIN;
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if (wanted == priv->cur_speed)
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return;
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div = dw_mci_exynos_get_ciu_div(host);
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ret = clk_set_rate(host->ciu_clk, wanted * div);
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if (ret)
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dev_warn(host->dev,
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"failed to set clk-rate %u error: %d\n",
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wanted * div, ret);
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actual = clk_get_rate(host->ciu_clk);
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host->bus_hz = actual / div;
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priv->cur_speed = wanted;
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host->current_speed = 0;
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}
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned int wanted = ios->clock;
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u32 timing = ios->timing, clksel;
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switch (timing) {
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case MMC_TIMING_MMC_HS400:
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/* Update tuned sample timing */
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clksel = SDMMC_CLKSEL_UP_SAMPLE(
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priv->hs400_timing, priv->tuned_sample);
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wanted <<= 1;
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break;
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case MMC_TIMING_MMC_DDR52:
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clksel = priv->ddr_timing;
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/* Should be double rate for DDR mode */
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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wanted <<= 1;
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break;
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default:
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clksel = priv->sdr_timing;
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}
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/* Set clock timing for the requested speed mode*/
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dw_mci_exynos_set_clksel_timing(host, clksel);
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/* Configure setting for HS400 */
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dw_mci_exynos_config_hs400(host, timing);
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/* Configure clock rate */
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dw_mci_exynos_adjust_clock(host, wanted);
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}
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static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv;
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struct device_node *np = host->dev->of_node;
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u32 timing[2];
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u32 div = 0;
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int idx;
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int ret;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
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if (of_device_is_compatible(np, exynos_compat[idx].compatible))
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priv->ctrl_type = exynos_compat[idx].ctrl_type;
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}
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
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else {
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of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
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priv->ciu_div = div;
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}
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-sdr-timing", timing, 2);
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if (ret)
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return ret;
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priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-ddr-timing", timing, 2);
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if (ret)
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return ret;
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priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-hs400-timing", timing, 2);
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if (!ret && of_property_read_u32(np,
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"samsung,read-strobe-delay", &priv->dqs_delay))
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dev_dbg(host->dev,
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"read-strobe-delay is not found, assuming usage of default value\n");
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priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
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HS400_FIXED_CIU_CLK_DIV);
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host->priv = priv;
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return 0;
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}
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static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
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else
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return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
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}
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static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
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{
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u32 clksel;
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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}
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static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 clksel;
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u8 sample;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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sample = (clksel + 1) & 0x7;
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clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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return sample;
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}
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static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
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{
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const u8 iter = 8;
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u8 __c;
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s8 i, loc = -1;
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for (i = 0; i < iter; i++) {
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__c = ror8(candiates, i);
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if ((__c & 0xc7) == 0xc7) {
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loc = i;
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goto out;
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}
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}
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for (i = 0; i < iter; i++) {
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__c = ror8(candiates, i);
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if ((__c & 0x83) == 0x83) {
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loc = i;
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goto out;
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}
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}
|
|
|
|
out:
|
|
return loc;
|
|
}
|
|
|
|
static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
|
|
{
|
|
struct dw_mci *host = slot->host;
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
|
struct mmc_host *mmc = slot->mmc;
|
|
u8 start_smpl, smpl, candiates = 0;
|
|
s8 found = -1;
|
|
int ret = 0;
|
|
|
|
start_smpl = dw_mci_exynos_get_clksmpl(host);
|
|
|
|
do {
|
|
mci_writel(host, TMOUT, ~0);
|
|
smpl = dw_mci_exynos_move_next_clksmpl(host);
|
|
|
|
if (!mmc_send_tuning(mmc, opcode, NULL))
|
|
candiates |= (1 << smpl);
|
|
|
|
} while (start_smpl != smpl);
|
|
|
|
found = dw_mci_exynos_get_best_clksmpl(candiates);
|
|
if (found >= 0) {
|
|
dw_mci_exynos_set_clksmpl(host, found);
|
|
priv->tuned_sample = found;
|
|
} else {
|
|
ret = -EIO;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
|
|
struct mmc_ios *ios)
|
|
{
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
|
|
|
dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
|
|
dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Common capabilities of Exynos4/Exynos5 SoC */
|
|
static unsigned long exynos_dwmmc_caps[4] = {
|
|
MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
|
|
MMC_CAP_CMD23,
|
|
MMC_CAP_CMD23,
|
|
MMC_CAP_CMD23,
|
|
};
|
|
|
|
static const struct dw_mci_drv_data exynos_drv_data = {
|
|
.caps = exynos_dwmmc_caps,
|
|
.init = dw_mci_exynos_priv_init,
|
|
.set_ios = dw_mci_exynos_set_ios,
|
|
.parse_dt = dw_mci_exynos_parse_dt,
|
|
.execute_tuning = dw_mci_exynos_execute_tuning,
|
|
.prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
|
|
};
|
|
|
|
static const struct of_device_id dw_mci_exynos_match[] = {
|
|
{ .compatible = "samsung,exynos4412-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos5250-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos5420-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos5420-dw-mshc-smu",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos7-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos7-dw-mshc-smu",
|
|
.data = &exynos_drv_data, },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
|
|
|
|
static int dw_mci_exynos_probe(struct platform_device *pdev)
|
|
{
|
|
const struct dw_mci_drv_data *drv_data;
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
|
|
drv_data = match->data;
|
|
return dw_mci_pltfm_register(pdev, drv_data);
|
|
}
|
|
|
|
static const struct dev_pm_ops dw_mci_exynos_pmops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
|
|
.resume_noirq = dw_mci_exynos_resume_noirq,
|
|
.thaw_noirq = dw_mci_exynos_resume_noirq,
|
|
.restore_noirq = dw_mci_exynos_resume_noirq,
|
|
};
|
|
|
|
static struct platform_driver dw_mci_exynos_pltfm_driver = {
|
|
.probe = dw_mci_exynos_probe,
|
|
.remove = dw_mci_pltfm_remove,
|
|
.driver = {
|
|
.name = "dwmmc_exynos",
|
|
.of_match_table = dw_mci_exynos_match,
|
|
.pm = &dw_mci_exynos_pmops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(dw_mci_exynos_pltfm_driver);
|
|
|
|
MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
|
|
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:dwmmc_exynos");
|