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![Mauro Carvalho Chehab](/assets/img/avatar_default.png)
Both mci.mem_is_per_rank and mci.csbased denote the same thing: the memory controller is csrows based. Merge both fields into one. There's no need for the driver to actually fill it, as the core detects it by checking if one of the layers has the csrows type as part of the memory hierarchy: if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) per_rank = true; Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Borislav Petkov <bp@suse.de>
745 lines
24 KiB
C
745 lines
24 KiB
C
/*
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* Generic EDAC defs
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*
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#ifndef _LINUX_EDAC_H_
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#define _LINUX_EDAC_H_
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#include <linux/atomic.h>
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#include <linux/device.h>
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#include <linux/completion.h>
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#include <linux/workqueue.h>
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#include <linux/debugfs.h>
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struct device;
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#define EDAC_OPSTATE_INVAL -1
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#define EDAC_OPSTATE_POLL 0
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#define EDAC_OPSTATE_NMI 1
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#define EDAC_OPSTATE_INT 2
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extern int edac_op_state;
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extern int edac_err_assert;
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extern atomic_t edac_handlers;
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extern struct bus_type edac_subsys;
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extern int edac_handler_set(void);
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extern void edac_atomic_assert_error(void);
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extern struct bus_type *edac_get_sysfs_subsys(void);
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extern void edac_put_sysfs_subsys(void);
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static inline void opstate_init(void)
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{
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switch (edac_op_state) {
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case EDAC_OPSTATE_POLL:
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case EDAC_OPSTATE_NMI:
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break;
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default:
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edac_op_state = EDAC_OPSTATE_POLL;
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}
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return;
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}
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/* Max length of a DIMM label*/
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#define EDAC_MC_LABEL_LEN 31
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/* Maximum size of the location string */
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#define LOCATION_SIZE 80
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/* Defines the maximum number of labels that can be reported */
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#define EDAC_MAX_LABELS 8
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/* String used to join two or more labels */
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#define OTHER_LABEL " or "
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/**
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* enum dev_type - describe the type of memory DRAM chips used at the stick
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* @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
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* @DEV_X1: 1 bit for data
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* @DEV_X2: 2 bits for data
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* @DEV_X4: 4 bits for data
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* @DEV_X8: 8 bits for data
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* @DEV_X16: 16 bits for data
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* @DEV_X32: 32 bits for data
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* @DEV_X64: 64 bits for data
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*
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* Typical values are x4 and x8.
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*/
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enum dev_type {
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DEV_UNKNOWN = 0,
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DEV_X1,
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DEV_X2,
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DEV_X4,
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DEV_X8,
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DEV_X16,
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DEV_X32, /* Do these parts exist? */
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DEV_X64 /* Do these parts exist? */
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};
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#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
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#define DEV_FLAG_X1 BIT(DEV_X1)
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#define DEV_FLAG_X2 BIT(DEV_X2)
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#define DEV_FLAG_X4 BIT(DEV_X4)
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#define DEV_FLAG_X8 BIT(DEV_X8)
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#define DEV_FLAG_X16 BIT(DEV_X16)
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#define DEV_FLAG_X32 BIT(DEV_X32)
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#define DEV_FLAG_X64 BIT(DEV_X64)
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/**
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* enum hw_event_mc_err_type - type of the detected error
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*
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* @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
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* corrected error was detected
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* @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
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* can't be corrected by ECC, but it is not
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* fatal (maybe it is on an unused memory area,
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* or the memory controller could recover from
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* it for example, by re-trying the operation).
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* @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
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* be recovered.
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*/
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enum hw_event_mc_err_type {
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HW_EVENT_ERR_CORRECTED,
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HW_EVENT_ERR_UNCORRECTED,
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HW_EVENT_ERR_FATAL,
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HW_EVENT_ERR_INFO,
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};
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static inline char *mc_event_error_type(const unsigned int err_type)
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{
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switch (err_type) {
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case HW_EVENT_ERR_CORRECTED:
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return "Corrected";
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case HW_EVENT_ERR_UNCORRECTED:
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return "Uncorrected";
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case HW_EVENT_ERR_FATAL:
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return "Fatal";
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default:
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case HW_EVENT_ERR_INFO:
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return "Info";
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}
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}
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/**
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* enum mem_type - memory types. For a more detailed reference, please see
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* http://en.wikipedia.org/wiki/DRAM
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*
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* @MEM_EMPTY Empty csrow
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* @MEM_RESERVED: Reserved csrow type
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* @MEM_UNKNOWN: Unknown csrow type
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* @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
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* @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
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* @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
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* @MEM_SDR: SDR - Single data rate SDRAM
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* http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
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* They use 3 pins for chip select: Pins 0 and 2 are
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* for rank 0; pins 1 and 3 are for rank 1, if the memory
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* is dual-rank.
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* @MEM_RDR: Registered SDR SDRAM
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* @MEM_DDR: Double data rate SDRAM
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* http://en.wikipedia.org/wiki/DDR_SDRAM
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* @MEM_RDDR: Registered Double data rate SDRAM
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* This is a variant of the DDR memories.
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* A registered memory has a buffer inside it, hiding
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* part of the memory details to the memory controller.
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* @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
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* @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
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* Those memories are labed as "PC2-" instead of "PC" to
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* differenciate from DDR.
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* @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
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* and JESD206.
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* Those memories are accessed per DIMM slot, and not by
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* a chip select signal.
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* @MEM_RDDR2: Registered DDR2 RAM
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* This is a variant of the DDR2 memories.
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* @MEM_XDR: Rambus XDR
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* It is an evolution of the original RAMBUS memories,
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* created to compete with DDR2. Weren't used on any
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* x86 arch, but cell_edac PPC memory controller uses it.
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* @MEM_DDR3: DDR3 RAM
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* @MEM_RDDR3: Registered DDR3 RAM
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* This is a variant of the DDR3 memories.
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*/
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enum mem_type {
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MEM_EMPTY = 0,
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MEM_RESERVED,
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MEM_UNKNOWN,
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MEM_FPM,
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MEM_EDO,
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MEM_BEDO,
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MEM_SDR,
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MEM_RDR,
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MEM_DDR,
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MEM_RDDR,
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MEM_RMBS,
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MEM_DDR2,
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MEM_FB_DDR2,
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MEM_RDDR2,
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MEM_XDR,
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MEM_DDR3,
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MEM_RDDR3,
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};
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#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
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#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
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#define MEM_FLAG_FPM BIT(MEM_FPM)
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#define MEM_FLAG_EDO BIT(MEM_EDO)
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#define MEM_FLAG_BEDO BIT(MEM_BEDO)
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#define MEM_FLAG_SDR BIT(MEM_SDR)
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#define MEM_FLAG_RDR BIT(MEM_RDR)
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#define MEM_FLAG_DDR BIT(MEM_DDR)
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#define MEM_FLAG_RDDR BIT(MEM_RDDR)
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#define MEM_FLAG_RMBS BIT(MEM_RMBS)
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#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
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#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
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#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
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#define MEM_FLAG_XDR BIT(MEM_XDR)
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#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
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#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
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/**
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* enum edac-type - Error Detection and Correction capabilities and mode
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* @EDAC_UNKNOWN: Unknown if ECC is available
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* @EDAC_NONE: Doesn't support ECC
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* @EDAC_RESERVED: Reserved ECC type
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* @EDAC_PARITY: Detects parity errors
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* @EDAC_EC: Error Checking - no correction
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* @EDAC_SECDED: Single bit error correction, Double detection
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* @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
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* @EDAC_S4ECD4ED: Chipkill x4 devices
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* @EDAC_S8ECD8ED: Chipkill x8 devices
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* @EDAC_S16ECD16ED: Chipkill x16 devices
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*/
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enum edac_type {
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EDAC_UNKNOWN = 0,
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EDAC_NONE,
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EDAC_RESERVED,
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EDAC_PARITY,
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EDAC_EC,
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EDAC_SECDED,
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EDAC_S2ECD2ED,
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EDAC_S4ECD4ED,
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EDAC_S8ECD8ED,
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EDAC_S16ECD16ED,
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};
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#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
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#define EDAC_FLAG_NONE BIT(EDAC_NONE)
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#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
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#define EDAC_FLAG_EC BIT(EDAC_EC)
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#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
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#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
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#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
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#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
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#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
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/**
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* enum scrub_type - scrubbing capabilities
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* @SCRUB_UNKNOWN Unknown if scrubber is available
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* @SCRUB_NONE: No scrubber
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* @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
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* @SCRUB_SW_SRC: Software scrub only errors
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* @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
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* @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
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* @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
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* @SCRUB_HW_SRC: Hardware scrub only errors
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* @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
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* SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
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*/
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enum scrub_type {
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SCRUB_UNKNOWN = 0,
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SCRUB_NONE,
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SCRUB_SW_PROG,
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SCRUB_SW_SRC,
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SCRUB_SW_PROG_SRC,
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SCRUB_SW_TUNABLE,
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SCRUB_HW_PROG,
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SCRUB_HW_SRC,
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SCRUB_HW_PROG_SRC,
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SCRUB_HW_TUNABLE
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};
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#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
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#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
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#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
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#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
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#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
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#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
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#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
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#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
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/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
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/* EDAC internal operation states */
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#define OP_ALLOC 0x100
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#define OP_RUNNING_POLL 0x201
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#define OP_RUNNING_INTERRUPT 0x202
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#define OP_RUNNING_POLL_INTR 0x203
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#define OP_OFFLINE 0x300
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/*
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* Concepts used at the EDAC subsystem
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*
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* There are several things to be aware of that aren't at all obvious:
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*
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* SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
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*
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* These are some of the many terms that are thrown about that don't always
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* mean what people think they mean (Inconceivable!). In the interest of
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* creating a common ground for discussion, terms and their definitions
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* will be established.
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*
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* Memory devices: The individual DRAM chips on a memory stick. These
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* devices commonly output 4 and 8 bits each (x4, x8).
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* Grouping several of these in parallel provides the
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* number of bits that the memory controller expects:
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* typically 72 bits, in order to provide 64 bits +
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* 8 bits of ECC data.
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*
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* Memory Stick: A printed circuit board that aggregates multiple
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* memory devices in parallel. In general, this is the
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* Field Replaceable Unit (FRU) which gets replaced, in
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* the case of excessive errors. Most often it is also
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* called DIMM (Dual Inline Memory Module).
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*
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* Memory Socket: A physical connector on the motherboard that accepts
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* a single memory stick. Also called as "slot" on several
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* datasheets.
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*
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* Channel: A memory controller channel, responsible to communicate
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* with a group of DIMMs. Each channel has its own
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* independent control (command) and data bus, and can
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* be used independently or grouped with other channels.
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*
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* Branch: It is typically the highest hierarchy on a
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* Fully-Buffered DIMM memory controller.
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* Typically, it contains two channels.
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* Two channels at the same branch can be used in single
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* mode or in lockstep mode.
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* When lockstep is enabled, the cacheline is doubled,
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* but it generally brings some performance penalty.
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* Also, it is generally not possible to point to just one
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* memory stick when an error occurs, as the error
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* correction code is calculated using two DIMMs instead
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* of one. Due to that, it is capable of correcting more
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* errors than on single mode.
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*
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* Single-channel: The data accessed by the memory controller is contained
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* into one dimm only. E. g. if the data is 64 bits-wide,
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* the data flows to the CPU using one 64 bits parallel
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* access.
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* Typically used with SDR, DDR, DDR2 and DDR3 memories.
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* FB-DIMM and RAMBUS use a different concept for channel,
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* so this concept doesn't apply there.
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*
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* Double-channel: The data size accessed by the memory controller is
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* interlaced into two dimms, accessed at the same time.
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* E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
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* the data flows to the CPU using a 128 bits parallel
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* access.
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*
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* Chip-select row: This is the name of the DRAM signal used to select the
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* DRAM ranks to be accessed. Common chip-select rows for
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* single channel are 64 bits, for dual channel 128 bits.
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* It may not be visible by the memory controller, as some
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* DIMM types have a memory buffer that can hide direct
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* access to it from the Memory Controller.
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*
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* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
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* Motherboards commonly drive two chip-select pins to
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* a memory stick. A single-ranked stick, will occupy
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* only one of those rows. The other will be unused.
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*
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* Double-Ranked stick: A double-ranked stick has two chip-select rows which
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently.
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*
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* Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
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* A double-sided stick has two chip-select rows which
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently. "Double-sided"
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* is irrespective of the memory devices being mounted
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* on both sides of the memory stick.
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*
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* Socket set: All of the memory sticks that are required for
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* a single memory access or all of the memory sticks
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* spanned by a chip-select row. A single socket set
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* has two chip-select rows and if double-sided sticks
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* are used these will occupy those chip-select rows.
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*
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* Bank: This term is avoided because it is unclear when
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* needing to distinguish between chip-select rows and
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* socket sets.
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*
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* Controller pages:
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*
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* Physical pages:
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*
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* Virtual pages:
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*
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*
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* STRUCTURE ORGANIZATION AND CHOICES
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*
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*
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*
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* PS - I enjoyed writing all that about as much as you enjoyed reading it.
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*/
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/**
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* enum edac_mc_layer - memory controller hierarchy layer
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*
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* @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
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* @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
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* @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
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* @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
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* @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
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* as a single memory area. This is used when
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* retrieving errors from a firmware driven driver.
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*
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* This enum is used by the drivers to tell edac_mc_sysfs what name should
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* be used when describing a memory stick location.
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*/
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enum edac_mc_layer_type {
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EDAC_MC_LAYER_BRANCH,
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EDAC_MC_LAYER_CHANNEL,
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EDAC_MC_LAYER_SLOT,
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EDAC_MC_LAYER_CHIP_SELECT,
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EDAC_MC_LAYER_ALL_MEM,
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};
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/**
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* struct edac_mc_layer - describes the memory controller hierarchy
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* @layer: layer type
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* @size: number of components per layer. For example,
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* if the channel layer has two channels, size = 2
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* @is_virt_csrow: This layer is part of the "csrow" when old API
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* compatibility mode is enabled. Otherwise, it is
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* a channel
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*/
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struct edac_mc_layer {
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enum edac_mc_layer_type type;
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unsigned size;
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bool is_virt_csrow;
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};
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/*
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* Maximum number of layers used by the memory controller to uniquely
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* identify a single memory stick.
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* NOTE: Changing this constant requires not only to change the constant
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* below, but also to change the existing code at the core, as there are
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* some code there that are optimized for 3 layers.
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*/
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#define EDAC_MAX_LAYERS 3
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/**
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* EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
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* for the element given by [layer0,layer1,layer2] position
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*
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* @layers: a struct edac_mc_layer array, describing how many elements
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* were allocated for each layer
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* @n_layers: Number of layers at the @layers array
|
|
* @layer0: layer0 position
|
|
* @layer1: layer1 position. Unused if n_layers < 2
|
|
* @layer2: layer2 position. Unused if n_layers < 3
|
|
*
|
|
* For 1 layer, this macro returns &var[layer0] - &var
|
|
* For 2 layers, this macro is similar to allocate a bi-dimensional array
|
|
* and to return "&var[layer0][layer1] - &var"
|
|
* For 3 layers, this macro is similar to allocate a tri-dimensional array
|
|
* and to return "&var[layer0][layer1][layer2] - &var"
|
|
*
|
|
* A loop could be used here to make it more generic, but, as we only have
|
|
* 3 layers, this is a little faster.
|
|
* By design, layers can never be 0 or more than 3. If that ever happens,
|
|
* a NULL is returned, causing an OOPS during the memory allocation routine,
|
|
* with would point to the developer that he's doing something wrong.
|
|
*/
|
|
#define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
|
|
int __i; \
|
|
if ((nlayers) == 1) \
|
|
__i = layer0; \
|
|
else if ((nlayers) == 2) \
|
|
__i = (layer1) + ((layers[1]).size * (layer0)); \
|
|
else if ((nlayers) == 3) \
|
|
__i = (layer2) + ((layers[2]).size * ((layer1) + \
|
|
((layers[1]).size * (layer0)))); \
|
|
else \
|
|
__i = -EINVAL; \
|
|
__i; \
|
|
})
|
|
|
|
/**
|
|
* EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
|
|
* for the element given by [layer0,layer1,layer2] position
|
|
*
|
|
* @layers: a struct edac_mc_layer array, describing how many elements
|
|
* were allocated for each layer
|
|
* @var: name of the var where we want to get the pointer
|
|
* (like mci->dimms)
|
|
* @n_layers: Number of layers at the @layers array
|
|
* @layer0: layer0 position
|
|
* @layer1: layer1 position. Unused if n_layers < 2
|
|
* @layer2: layer2 position. Unused if n_layers < 3
|
|
*
|
|
* For 1 layer, this macro returns &var[layer0]
|
|
* For 2 layers, this macro is similar to allocate a bi-dimensional array
|
|
* and to return "&var[layer0][layer1]"
|
|
* For 3 layers, this macro is similar to allocate a tri-dimensional array
|
|
* and to return "&var[layer0][layer1][layer2]"
|
|
*/
|
|
#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
|
|
typeof(*var) __p; \
|
|
int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
|
|
if (___i < 0) \
|
|
__p = NULL; \
|
|
else \
|
|
__p = (var)[___i]; \
|
|
__p; \
|
|
})
|
|
|
|
struct dimm_info {
|
|
struct device dev;
|
|
|
|
char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
|
|
|
|
/* Memory location data */
|
|
unsigned location[EDAC_MAX_LAYERS];
|
|
|
|
struct mem_ctl_info *mci; /* the parent */
|
|
|
|
u32 grain; /* granularity of reported error in bytes */
|
|
enum dev_type dtype; /* memory device type */
|
|
enum mem_type mtype; /* memory dimm type */
|
|
enum edac_type edac_mode; /* EDAC mode for this dimm */
|
|
|
|
u32 nr_pages; /* number of pages on this dimm */
|
|
|
|
unsigned csrow, cschannel; /* Points to the old API data */
|
|
};
|
|
|
|
/**
|
|
* struct rank_info - contains the information for one DIMM rank
|
|
*
|
|
* @chan_idx: channel number where the rank is (typically, 0 or 1)
|
|
* @ce_count: number of correctable errors for this rank
|
|
* @csrow: A pointer to the chip select row structure (the parent
|
|
* structure). The location of the rank is given by
|
|
* the (csrow->csrow_idx, chan_idx) vector.
|
|
* @dimm: A pointer to the DIMM structure, where the DIMM label
|
|
* information is stored.
|
|
*
|
|
* FIXME: Currently, the EDAC core model will assume one DIMM per rank.
|
|
* This is a bad assumption, but it makes this patch easier. Later
|
|
* patches in this series will fix this issue.
|
|
*/
|
|
struct rank_info {
|
|
int chan_idx;
|
|
struct csrow_info *csrow;
|
|
struct dimm_info *dimm;
|
|
|
|
u32 ce_count; /* Correctable Errors for this csrow */
|
|
};
|
|
|
|
struct csrow_info {
|
|
struct device dev;
|
|
|
|
/* Used only by edac_mc_find_csrow_by_page() */
|
|
unsigned long first_page; /* first page number in csrow */
|
|
unsigned long last_page; /* last page number in csrow */
|
|
unsigned long page_mask; /* used for interleaving -
|
|
* 0UL for non intlv */
|
|
|
|
int csrow_idx; /* the chip-select row */
|
|
|
|
u32 ue_count; /* Uncorrectable Errors for this csrow */
|
|
u32 ce_count; /* Correctable Errors for this csrow */
|
|
|
|
struct mem_ctl_info *mci; /* the parent */
|
|
|
|
/* channel information for this csrow */
|
|
u32 nr_channels;
|
|
struct rank_info **channels;
|
|
};
|
|
|
|
/*
|
|
* struct errcount_attribute - used to store the several error counts
|
|
*/
|
|
struct errcount_attribute_data {
|
|
int n_layers;
|
|
int pos[EDAC_MAX_LAYERS];
|
|
int layer0, layer1, layer2;
|
|
};
|
|
|
|
/**
|
|
* edac_raw_error_desc - Raw error report structure
|
|
* @grain: minimum granularity for an error report, in bytes
|
|
* @error_count: number of errors of the same type
|
|
* @top_layer: top layer of the error (layer[0])
|
|
* @mid_layer: middle layer of the error (layer[1])
|
|
* @low_layer: low layer of the error (layer[2])
|
|
* @page_frame_number: page where the error happened
|
|
* @offset_in_page: page offset
|
|
* @syndrome: syndrome of the error (or 0 if unknown or if
|
|
* the syndrome is not applicable)
|
|
* @msg: error message
|
|
* @location: location of the error
|
|
* @label: label of the affected DIMM(s)
|
|
* @other_detail: other driver-specific detail about the error
|
|
* @enable_per_layer_report: if false, the error affects all layers
|
|
* (typically, a memory controller error)
|
|
*/
|
|
struct edac_raw_error_desc {
|
|
/*
|
|
* NOTE: everything before grain won't be cleaned by
|
|
* edac_raw_error_desc_clean()
|
|
*/
|
|
char location[LOCATION_SIZE];
|
|
char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
|
|
long grain;
|
|
|
|
/* the vars below and grain will be cleaned on every new error report */
|
|
u16 error_count;
|
|
int top_layer;
|
|
int mid_layer;
|
|
int low_layer;
|
|
unsigned long page_frame_number;
|
|
unsigned long offset_in_page;
|
|
unsigned long syndrome;
|
|
const char *msg;
|
|
const char *other_detail;
|
|
bool enable_per_layer_report;
|
|
};
|
|
|
|
/* MEMORY controller information structure
|
|
*/
|
|
struct mem_ctl_info {
|
|
struct device dev;
|
|
struct bus_type bus;
|
|
|
|
struct list_head link; /* for global list of mem_ctl_info structs */
|
|
|
|
struct module *owner; /* Module owner of this control struct */
|
|
|
|
unsigned long mtype_cap; /* memory types supported by mc */
|
|
unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
|
|
unsigned long edac_cap; /* configuration capabilities - this is
|
|
* closely related to edac_ctl_cap. The
|
|
* difference is that the controller may be
|
|
* capable of s4ecd4ed which would be listed
|
|
* in edac_ctl_cap, but if channels aren't
|
|
* capable of s4ecd4ed then the edac_cap would
|
|
* not have that capability.
|
|
*/
|
|
unsigned long scrub_cap; /* chipset scrub capabilities */
|
|
enum scrub_type scrub_mode; /* current scrub mode */
|
|
|
|
/* Translates sdram memory scrub rate given in bytes/sec to the
|
|
internal representation and configures whatever else needs
|
|
to be configured.
|
|
*/
|
|
int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
|
|
|
|
/* Get the current sdram memory scrub rate from the internal
|
|
representation and converts it to the closest matching
|
|
bandwidth in bytes/sec.
|
|
*/
|
|
int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
|
|
|
|
|
|
/* pointer to edac checking routine */
|
|
void (*edac_check) (struct mem_ctl_info * mci);
|
|
|
|
/*
|
|
* Remaps memory pages: controller pages to physical pages.
|
|
* For most MC's, this will be NULL.
|
|
*/
|
|
/* FIXME - why not send the phys page to begin with? */
|
|
unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
|
|
unsigned long page);
|
|
int mc_idx;
|
|
struct csrow_info **csrows;
|
|
unsigned nr_csrows, num_cschannel;
|
|
|
|
/*
|
|
* Memory Controller hierarchy
|
|
*
|
|
* There are basically two types of memory controller: the ones that
|
|
* sees memory sticks ("dimms"), and the ones that sees memory ranks.
|
|
* All old memory controllers enumerate memories per rank, but most
|
|
* of the recent drivers enumerate memories per DIMM, instead.
|
|
* When the memory controller is per rank, csbased is true.
|
|
*/
|
|
unsigned n_layers;
|
|
struct edac_mc_layer *layers;
|
|
bool csbased;
|
|
|
|
/*
|
|
* DIMM info. Will eventually remove the entire csrows_info some day
|
|
*/
|
|
unsigned tot_dimms;
|
|
struct dimm_info **dimms;
|
|
|
|
/*
|
|
* FIXME - what about controllers on other busses? - IDs must be
|
|
* unique. dev pointer should be sufficiently unique, but
|
|
* BUS:SLOT.FUNC numbers may not be unique.
|
|
*/
|
|
struct device *pdev;
|
|
const char *mod_name;
|
|
const char *mod_ver;
|
|
const char *ctl_name;
|
|
const char *dev_name;
|
|
void *pvt_info;
|
|
unsigned long start_time; /* mci load start time (in jiffies) */
|
|
|
|
/*
|
|
* drivers shouldn't access those fields directly, as the core
|
|
* already handles that.
|
|
*/
|
|
u32 ce_noinfo_count, ue_noinfo_count;
|
|
u32 ue_mc, ce_mc;
|
|
u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
|
|
|
|
struct completion complete;
|
|
|
|
/* Additional top controller level attributes, but specified
|
|
* by the low level driver.
|
|
*
|
|
* Set by the low level driver to provide attributes at the
|
|
* controller level.
|
|
* An array of structures, NULL terminated
|
|
*
|
|
* If attributes are desired, then set to array of attributes
|
|
* If no attributes are desired, leave NULL
|
|
*/
|
|
const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
|
|
|
|
/* work struct for this MC */
|
|
struct delayed_work work;
|
|
|
|
/*
|
|
* Used to report an error - by being at the global struct
|
|
* makes the memory allocated by the EDAC core
|
|
*/
|
|
struct edac_raw_error_desc error_desc;
|
|
|
|
/* the internal state of this controller instance */
|
|
int op_state;
|
|
|
|
#ifdef CONFIG_EDAC_DEBUG
|
|
struct dentry *debugfs;
|
|
u8 fake_inject_layer[EDAC_MAX_LAYERS];
|
|
u32 fake_inject_ue;
|
|
u16 fake_inject_count;
|
|
#endif
|
|
};
|
|
|
|
#endif
|