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![Doug Anderson](/assets/img/avatar_default.png)
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up looping around forever. This has been seen to happen on exynos5420 silicon despite the fact that we haven't enabled any wakeup events due to a silicon errata. It is safe to do on all exynos variants. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
263 lines
7.3 KiB
C
263 lines
7.3 KiB
C
/*
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* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2012, Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define NUM_PINS(x) (x + 2)
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#define SDMMC_CLKSEL 0x09C
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#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
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#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
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#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
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#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
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#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
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SDMMC_CLKSEL_CCLK_DRIVE(y) | \
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SDMMC_CLKSEL_CCLK_DIVIDER(z))
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#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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/* Variations in Exynos specific dw-mshc controller */
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enum dw_mci_exynos_type {
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4412,
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DW_MCI_TYPE_EXYNOS5250,
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DW_MCI_TYPE_EXYNOS5420,
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};
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/* Exynos implementation specific driver private data */
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struct dw_mci_exynos_priv_data {
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enum dw_mci_exynos_type ctrl_type;
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u8 ciu_div;
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u32 sdr_timing;
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u32 ddr_timing;
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};
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static struct dw_mci_exynos_compatible {
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char *compatible;
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enum dw_mci_exynos_type ctrl_type;
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} exynos_compat[] = {
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{
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.compatible = "samsung,exynos4210-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
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}, {
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.compatible = "samsung,exynos4412-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
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}, {
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.compatible = "samsung,exynos5250-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
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}, {
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.compatible = "samsung,exynos5420-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
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},
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};
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static int dw_mci_exynos_priv_init(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv;
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int idx;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(host->dev, "mem alloc failed for private data\n");
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return -ENOMEM;
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}
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for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
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if (of_device_is_compatible(host->dev->of_node,
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exynos_compat[idx].compatible))
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priv->ctrl_type = exynos_compat[idx].ctrl_type;
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}
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host->priv = priv;
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return 0;
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}
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static int dw_mci_exynos_setup_clock(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420)
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host->bus_hz /= (priv->ciu_div + 1);
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int dw_mci_exynos_suspend(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_suspend(host);
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}
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static int dw_mci_exynos_resume(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_resume(host);
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}
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/**
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* dw_mci_exynos_resume_noirq - Exynos-specific resume code
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*
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* On exynos5420 there is a silicon errata that will sometimes leave the
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* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
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* that it fired and we can clear it by writing a 1 back. Clear it to prevent
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* interrupts from going off constantly.
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*
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* We run this code on all exynos variants because it doesn't hurt.
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*/
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static int dw_mci_exynos_resume_noirq(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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u32 clksel;
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clksel = mci_readl(host, CLKSEL);
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if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
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mci_writel(host, CLKSEL, clksel);
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return 0;
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}
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#else
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#define dw_mci_exynos_suspend NULL
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#define dw_mci_exynos_resume NULL
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#define dw_mci_exynos_resume_noirq NULL
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#endif /* CONFIG_PM_SLEEP */
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static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
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{
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/*
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* Exynos4412 and Exynos5250 extends the use of CMD register with the
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* use of bit 29 (which is reserved on standard MSHC controllers) for
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* optionally bypassing the HOLD register for command and data. The
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* HOLD register should be bypassed in case there is no phase shift
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* applied on CMD/DATA that is sent to the card.
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*/
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if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
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*cmdr |= SDMMC_CMD_USE_HOLD_REG;
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}
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (ios->timing == MMC_TIMING_UHS_DDR50)
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mci_writel(host, CLKSEL, priv->ddr_timing);
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else
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mci_writel(host, CLKSEL, priv->sdr_timing);
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}
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static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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struct device_node *np = host->dev->of_node;
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u32 timing[2];
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u32 div = 0;
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int ret;
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of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
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priv->ciu_div = div;
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-sdr-timing", timing, 2);
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if (ret)
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return ret;
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priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-ddr-timing", timing, 2);
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if (ret)
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return ret;
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priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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return 0;
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}
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/* Common capabilities of Exynos4/Exynos5 SoC */
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static unsigned long exynos_dwmmc_caps[4] = {
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MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
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MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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};
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static const struct dw_mci_drv_data exynos_drv_data = {
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.caps = exynos_dwmmc_caps,
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.init = dw_mci_exynos_priv_init,
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.setup_clock = dw_mci_exynos_setup_clock,
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.prepare_command = dw_mci_exynos_prepare_command,
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.set_ios = dw_mci_exynos_set_ios,
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.parse_dt = dw_mci_exynos_parse_dt,
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};
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static const struct of_device_id dw_mci_exynos_match[] = {
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{ .compatible = "samsung,exynos4412-dw-mshc",
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.data = &exynos_drv_data, },
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{ .compatible = "samsung,exynos5250-dw-mshc",
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.data = &exynos_drv_data, },
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{ .compatible = "samsung,exynos5420-dw-mshc",
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.data = &exynos_drv_data, },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
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static int dw_mci_exynos_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
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drv_data = match->data;
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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const struct dev_pm_ops dw_mci_exynos_pmops = {
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SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
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.resume_noirq = dw_mci_exynos_resume_noirq,
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.thaw_noirq = dw_mci_exynos_resume_noirq,
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.restore_noirq = dw_mci_exynos_resume_noirq,
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};
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static struct platform_driver dw_mci_exynos_pltfm_driver = {
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.probe = dw_mci_exynos_probe,
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.remove = __exit_p(dw_mci_pltfm_remove),
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.driver = {
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.name = "dwmmc_exynos",
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.of_match_table = dw_mci_exynos_match,
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.pm = &dw_mci_exynos_pmops,
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},
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};
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module_platform_driver(dw_mci_exynos_pltfm_driver);
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MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
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MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dwmmc-exynos");
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