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7f10074474
The PCIe controller in Tegra194 SoC is not ECAM-compliant. With the current hardware design, ECAM can be enabled only for one controller (the C5 controller) with bus numbers starting from 160 instead of 0. A different approach is taken to avoid this abnormal way of enabling ECAM for just one controller but to enable configuration space access for all the other controllers. In this approach, ops are added through MCFG quirk mechanism which access the configuration spaces by dynamically programming iATU (internal AddressTranslation Unit) to generate respective configuration accesses just like the way it is done in DesignWare core sub-system. This issue is specific to Tegra194 and it would be fixed in the future generations of Tegra SoCs. Link: https://lore.kernel.org/r/20210416134537.19474-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
311 lines
9.1 KiB
C
311 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016 Broadcom
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* Author: Jayachandran C <jchandra@broadcom.com>
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* Copyright (C) 2016 Semihalf
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* Author: Tomasz Nowicki <tn@semihalf.com>
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*/
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#define pr_fmt(fmt) "ACPI: " fmt
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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/* Structure to hold entries from the MCFG table */
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struct mcfg_entry {
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struct list_head list;
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phys_addr_t addr;
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u16 segment;
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u8 bus_start;
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u8 bus_end;
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};
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#ifdef CONFIG_PCI_QUIRKS
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struct mcfg_fixup {
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char oem_id[ACPI_OEM_ID_SIZE + 1];
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char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
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u32 oem_revision;
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u16 segment;
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struct resource bus_range;
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const struct pci_ecam_ops *ops;
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struct resource cfgres;
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};
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#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
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((end) - (start) + 1), \
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NULL, IORESOURCE_BUS)
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#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
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static struct mcfg_fixup mcfg_quirks[] = {
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/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
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#define AL_ECAM(table_id, rev, seg, ops) \
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{ "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
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AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
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AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
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AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
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AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
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AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
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AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
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AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
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AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
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#define QCOM_ECAM32(seg) \
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{ "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
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QCOM_ECAM32(0),
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QCOM_ECAM32(1),
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QCOM_ECAM32(2),
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QCOM_ECAM32(3),
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QCOM_ECAM32(4),
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QCOM_ECAM32(5),
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QCOM_ECAM32(6),
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QCOM_ECAM32(7),
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#define HISI_QUAD_DOM(table_id, seg, ops) \
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{ "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
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{ "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
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{ "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
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{ "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
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HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
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HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
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HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
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HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
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HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
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HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
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#define THUNDER_PEM_RES(addr, node) \
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DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
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#define THUNDER_PEM_QUIRK(rev, node) \
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{ "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
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{ "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
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{ "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
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{ "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
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{ "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
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{ "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
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#define THUNDER_ECAM_QUIRK(rev, seg) \
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{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
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&pci_thunder_ecam_ops }
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/* SoC pass2.x */
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THUNDER_PEM_QUIRK(1, 0),
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THUNDER_PEM_QUIRK(1, 1),
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THUNDER_ECAM_QUIRK(1, 10),
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/* SoC pass1.x */
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THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
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THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
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THUNDER_ECAM_QUIRK(2, 0),
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THUNDER_ECAM_QUIRK(2, 1),
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THUNDER_ECAM_QUIRK(2, 2),
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THUNDER_ECAM_QUIRK(2, 3),
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THUNDER_ECAM_QUIRK(2, 10),
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THUNDER_ECAM_QUIRK(2, 11),
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THUNDER_ECAM_QUIRK(2, 12),
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THUNDER_ECAM_QUIRK(2, 13),
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{ "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
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{ "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
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{ "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
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{ "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
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{ "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
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{ "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
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#define XGENE_V1_ECAM_MCFG(rev, seg) \
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{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
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&xgene_v1_pcie_ecam_ops }
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#define XGENE_V2_ECAM_MCFG(rev, seg) \
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{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
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&xgene_v2_pcie_ecam_ops }
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/* X-Gene SoC with v1 PCIe controller */
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XGENE_V1_ECAM_MCFG(1, 0),
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XGENE_V1_ECAM_MCFG(1, 1),
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XGENE_V1_ECAM_MCFG(1, 2),
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XGENE_V1_ECAM_MCFG(1, 3),
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XGENE_V1_ECAM_MCFG(1, 4),
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XGENE_V1_ECAM_MCFG(2, 0),
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XGENE_V1_ECAM_MCFG(2, 1),
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XGENE_V1_ECAM_MCFG(2, 2),
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XGENE_V1_ECAM_MCFG(2, 3),
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XGENE_V1_ECAM_MCFG(2, 4),
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/* X-Gene SoC with v2.1 PCIe controller */
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XGENE_V2_ECAM_MCFG(3, 0),
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XGENE_V2_ECAM_MCFG(3, 1),
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/* X-Gene SoC with v2.2 PCIe controller */
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XGENE_V2_ECAM_MCFG(4, 0),
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XGENE_V2_ECAM_MCFG(4, 1),
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XGENE_V2_ECAM_MCFG(4, 2),
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#define ALTRA_ECAM_QUIRK(rev, seg) \
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{ "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
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ALTRA_ECAM_QUIRK(1, 0),
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ALTRA_ECAM_QUIRK(1, 1),
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ALTRA_ECAM_QUIRK(1, 2),
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ALTRA_ECAM_QUIRK(1, 3),
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ALTRA_ECAM_QUIRK(1, 4),
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ALTRA_ECAM_QUIRK(1, 5),
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ALTRA_ECAM_QUIRK(1, 6),
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ALTRA_ECAM_QUIRK(1, 7),
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ALTRA_ECAM_QUIRK(1, 8),
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ALTRA_ECAM_QUIRK(1, 9),
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ALTRA_ECAM_QUIRK(1, 10),
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ALTRA_ECAM_QUIRK(1, 11),
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ALTRA_ECAM_QUIRK(1, 12),
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ALTRA_ECAM_QUIRK(1, 13),
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ALTRA_ECAM_QUIRK(1, 14),
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ALTRA_ECAM_QUIRK(1, 15),
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};
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static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
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static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
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static u32 mcfg_oem_revision;
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static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
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struct resource *bus_range)
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{
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if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
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!memcmp(f->oem_table_id, mcfg_oem_table_id,
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ACPI_OEM_TABLE_ID_SIZE) &&
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f->oem_revision == mcfg_oem_revision &&
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f->segment == segment &&
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resource_contains(&f->bus_range, bus_range))
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return 1;
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return 0;
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}
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#endif
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static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
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struct resource *cfgres,
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const struct pci_ecam_ops **ecam_ops)
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{
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#ifdef CONFIG_PCI_QUIRKS
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u16 segment = root->segment;
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struct resource *bus_range = &root->secondary;
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struct mcfg_fixup *f;
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int i;
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for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
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if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
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if (f->cfgres.start)
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*cfgres = f->cfgres;
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if (f->ops)
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*ecam_ops = f->ops;
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dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
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cfgres, bus_range, *ecam_ops);
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return;
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}
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}
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#endif
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}
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/* List to save MCFG entries */
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static LIST_HEAD(pci_mcfg_list);
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int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
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const struct pci_ecam_ops **ecam_ops)
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{
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const struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
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struct resource *bus_res = &root->secondary;
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u16 seg = root->segment;
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struct mcfg_entry *e;
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struct resource res;
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/* Use address from _CBA if present, otherwise lookup MCFG */
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if (root->mcfg_addr)
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goto skip_lookup;
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/*
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* We expect the range in bus_res in the coverage of MCFG bus range.
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*/
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list_for_each_entry(e, &pci_mcfg_list, list) {
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if (e->segment == seg && e->bus_start <= bus_res->start &&
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e->bus_end >= bus_res->end) {
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root->mcfg_addr = e->addr;
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}
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}
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skip_lookup:
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memset(&res, 0, sizeof(res));
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if (root->mcfg_addr) {
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res.start = root->mcfg_addr + (bus_res->start << 20);
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res.end = res.start + (resource_size(bus_res) << 20) - 1;
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res.flags = IORESOURCE_MEM;
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}
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/*
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* Allow quirks to override default ECAM ops and CFG resource
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* range. This may even fabricate a CFG resource range in case
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* MCFG does not have it. Invalid CFG start address means MCFG
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* firmware bug or we need another quirk in array.
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*/
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pci_mcfg_apply_quirks(root, &res, &ops);
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if (!res.start)
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return -ENXIO;
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*cfgres = res;
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*ecam_ops = ops;
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return 0;
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}
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static __init int pci_mcfg_parse(struct acpi_table_header *header)
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{
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struct acpi_table_mcfg *mcfg;
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struct acpi_mcfg_allocation *mptr;
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struct mcfg_entry *e, *arr;
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int i, n;
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if (header->length < sizeof(struct acpi_table_mcfg))
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return -EINVAL;
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n = (header->length - sizeof(struct acpi_table_mcfg)) /
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sizeof(struct acpi_mcfg_allocation);
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mcfg = (struct acpi_table_mcfg *)header;
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mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
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arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
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if (!arr)
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return -ENOMEM;
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for (i = 0, e = arr; i < n; i++, mptr++, e++) {
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e->segment = mptr->pci_segment;
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e->addr = mptr->address;
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e->bus_start = mptr->start_bus_number;
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e->bus_end = mptr->end_bus_number;
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list_add(&e->list, &pci_mcfg_list);
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}
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#ifdef CONFIG_PCI_QUIRKS
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/* Save MCFG IDs and revision for quirks matching */
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memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
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memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
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mcfg_oem_revision = header->oem_revision;
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#endif
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pr_info("MCFG table detected, %d entries\n", n);
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return 0;
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}
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/* Interface called by ACPI - parse and save MCFG table */
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void __init pci_mmcfg_late_init(void)
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{
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int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
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if (err)
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pr_debug("Failed to parse MCFG (%d)\n", err);
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}
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