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2c1966af07
Add a platform driver for the i.MX8MM SoC describing bus topology. Bandwidth adjustments is currently only supported on the DDRC and main NOC. Scaling for the vpu/gpu/display NICs could be added in the future. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Link: https://lore.kernel.org/r/b14eef179dbd837a486619724b8033490f49db72.1586174566.git.leonard.crestez@nxp.com Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
105 lines
3.5 KiB
C
105 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Interconnect framework driver for i.MX8MM SoC
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*
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* Copyright (c) 2019, BayLibre
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* Copyright (c) 2019-2020, NXP
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* Author: Alexandre Bailon <abailon@baylibre.com>
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* Author: Leonard Crestez <leonard.crestez@nxp.com>
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/interconnect/imx8mm.h>
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#include "imx.h"
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static const struct imx_icc_node_adj_desc imx8mm_dram_adj = {
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.bw_mul = 1,
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.bw_div = 16,
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.phandle_name = "fsl,ddrc",
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};
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static const struct imx_icc_node_adj_desc imx8mm_noc_adj = {
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.bw_mul = 1,
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.bw_div = 16,
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.main_noc = true,
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};
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/*
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* Describe bus masters, slaves and connections between them
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*
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* This is a simplified subset of the bus diagram, there are several other
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* PL301 nics which are skipped/merged into PL301_MAIN
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*/
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static struct imx_icc_node_desc nodes[] = {
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DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj,
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IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN),
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DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj),
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DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL),
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DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC),
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/* VPUMIX */
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DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO),
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DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO),
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DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO),
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DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC),
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/* GPUMIX */
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DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU),
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DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU),
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DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC),
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/* DISPLAYMIX */
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DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI),
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DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI),
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DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC),
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/* HSIO */
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DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO),
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DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO),
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DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO),
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DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC),
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/* Audio */
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DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO),
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DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO),
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DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN),
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/* Ethernet */
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DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET),
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DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN),
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/* Other */
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DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN),
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DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN),
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DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN),
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DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN),
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DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN),
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DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL,
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IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM),
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};
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static int imx8mm_icc_probe(struct platform_device *pdev)
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{
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return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes));
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}
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static int imx8mm_icc_remove(struct platform_device *pdev)
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{
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return imx_icc_unregister(pdev);
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}
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static struct platform_driver imx8mm_icc_driver = {
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.probe = imx8mm_icc_probe,
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.remove = imx8mm_icc_remove,
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.driver = {
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.name = "imx8mm-interconnect",
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},
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};
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module_platform_driver(imx8mm_icc_driver);
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MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:imx8mm-interconnect");
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