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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
230 lines
5.7 KiB
C
230 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
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*
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* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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/* LPC18xx RGU registers */
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#define LPC18XX_RGU_CTRL0 0x100
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#define LPC18XX_RGU_CTRL1 0x104
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#define LPC18XX_RGU_ACTIVE_STATUS0 0x150
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#define LPC18XX_RGU_ACTIVE_STATUS1 0x154
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#define LPC18XX_RGU_RESETS_PER_REG 32
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/* Internal reset outputs */
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#define LPC18XX_RGU_CORE_RST 0
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#define LPC43XX_RGU_M0SUB_RST 12
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#define LPC43XX_RGU_M0APP_RST 56
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struct lpc18xx_rgu_data {
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struct reset_controller_dev rcdev;
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struct notifier_block restart_nb;
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struct clk *clk_delay;
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struct clk *clk_reg;
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void __iomem *base;
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spinlock_t lock;
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u32 delay_us;
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};
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#define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev)
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static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode,
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void *cmd)
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{
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struct lpc18xx_rgu_data *rc = container_of(nb, struct lpc18xx_rgu_data,
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restart_nb);
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writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0);
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mdelay(2000);
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pr_emerg("%s: unable to restart system\n", __func__);
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return NOTIFY_DONE;
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}
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/*
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* The LPC18xx RGU has mostly self-deasserting resets except for the
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* two reset lines going to the internal Cortex-M0 cores.
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*
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* To prevent the M0 core resets from accidentally getting deasserted
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* status register must be check and bits in control register set to
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* preserve the state.
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*/
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static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev,
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unsigned long id, bool set)
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{
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struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
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u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0;
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u32 ctrl_offset = LPC18XX_RGU_CTRL0;
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unsigned long flags;
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u32 stat, rst_bit;
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stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
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ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
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rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
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spin_lock_irqsave(&rc->lock, flags);
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stat = ~readl(rc->base + stat_offset);
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if (set)
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writel(stat | rst_bit, rc->base + ctrl_offset);
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else
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writel(stat & ~rst_bit, rc->base + ctrl_offset);
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spin_unlock_irqrestore(&rc->lock, flags);
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return 0;
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}
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static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return lpc18xx_rgu_setclear_reset(rcdev, id, true);
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}
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static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return lpc18xx_rgu_setclear_reset(rcdev, id, false);
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}
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/* Only M0 cores require explicit reset deassert */
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static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
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lpc18xx_rgu_assert(rcdev, id);
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udelay(rc->delay_us);
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switch (id) {
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case LPC43XX_RGU_M0SUB_RST:
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case LPC43XX_RGU_M0APP_RST:
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lpc18xx_rgu_setclear_reset(rcdev, id, false);
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}
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return 0;
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}
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static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
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u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0;
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offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
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bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
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return !(readl(rc->base + offset) & bit);
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}
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static const struct reset_control_ops lpc18xx_rgu_ops = {
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.reset = lpc18xx_rgu_reset,
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.assert = lpc18xx_rgu_assert,
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.deassert = lpc18xx_rgu_deassert,
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.status = lpc18xx_rgu_status,
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};
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static int lpc18xx_rgu_probe(struct platform_device *pdev)
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{
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struct lpc18xx_rgu_data *rc;
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struct resource *res;
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u32 fcclk, firc;
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int ret;
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rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
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if (!rc)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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rc->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(rc->base))
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return PTR_ERR(rc->base);
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rc->clk_reg = devm_clk_get(&pdev->dev, "reg");
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if (IS_ERR(rc->clk_reg)) {
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dev_err(&pdev->dev, "reg clock not found\n");
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return PTR_ERR(rc->clk_reg);
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}
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rc->clk_delay = devm_clk_get(&pdev->dev, "delay");
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if (IS_ERR(rc->clk_delay)) {
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dev_err(&pdev->dev, "delay clock not found\n");
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return PTR_ERR(rc->clk_delay);
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}
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ret = clk_prepare_enable(rc->clk_reg);
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if (ret) {
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dev_err(&pdev->dev, "unable to enable reg clock\n");
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return ret;
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}
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ret = clk_prepare_enable(rc->clk_delay);
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if (ret) {
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dev_err(&pdev->dev, "unable to enable delay clock\n");
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goto dis_clk_reg;
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}
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fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC;
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firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC;
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if (fcclk == 0 || firc == 0)
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rc->delay_us = 2;
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else
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rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc);
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spin_lock_init(&rc->lock);
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rc->rcdev.owner = THIS_MODULE;
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rc->rcdev.nr_resets = 64;
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rc->rcdev.ops = &lpc18xx_rgu_ops;
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rc->rcdev.of_node = pdev->dev.of_node;
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platform_set_drvdata(pdev, rc);
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ret = reset_controller_register(&rc->rcdev);
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if (ret) {
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dev_err(&pdev->dev, "unable to register device\n");
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goto dis_clks;
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}
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rc->restart_nb.priority = 192,
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rc->restart_nb.notifier_call = lpc18xx_rgu_restart,
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ret = register_restart_handler(&rc->restart_nb);
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if (ret)
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dev_warn(&pdev->dev, "failed to register restart handler\n");
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return 0;
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dis_clks:
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clk_disable_unprepare(rc->clk_delay);
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dis_clk_reg:
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clk_disable_unprepare(rc->clk_reg);
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return ret;
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}
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static const struct of_device_id lpc18xx_rgu_match[] = {
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{ .compatible = "nxp,lpc1850-rgu" },
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{ }
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};
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static struct platform_driver lpc18xx_rgu_driver = {
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.probe = lpc18xx_rgu_probe,
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.driver = {
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.name = "lpc18xx-reset",
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.of_match_table = lpc18xx_rgu_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(lpc18xx_rgu_driver);
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