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5f97f7f940
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
289 lines
6.6 KiB
C
289 lines
6.6 KiB
C
/*
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* System Manager driver for AT32AP CPUs
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/random.h>
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#include <linux/spinlock.h>
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#include <asm/intc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/arch/sm.h>
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#include "sm.h"
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#define SM_EIM_IRQ_RESOURCE 1
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#define SM_PM_IRQ_RESOURCE 2
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#define SM_RTC_IRQ_RESOURCE 3
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#define to_eim(irqc) container_of(irqc, struct at32_sm, irqc)
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struct at32_sm system_manager;
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int __init at32_sm_init(void)
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{
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struct resource *regs;
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struct at32_sm *sm = &system_manager;
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int ret = -ENXIO;
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regs = platform_get_resource(&at32_sm_device, IORESOURCE_MEM, 0);
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if (!regs)
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goto fail;
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spin_lock_init(&sm->lock);
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sm->pdev = &at32_sm_device;
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ret = -ENOMEM;
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sm->regs = ioremap(regs->start, regs->end - regs->start + 1);
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if (!sm->regs)
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goto fail;
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return 0;
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fail:
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printk(KERN_ERR "Failed to initialize System Manager: %d\n", ret);
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return ret;
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}
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/*
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* External Interrupt Module (EIM).
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*
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* EIM gets level- or edge-triggered interrupts of either polarity
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* from the outside and converts it to active-high level-triggered
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* interrupts that the internal interrupt controller can handle. EIM
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* also provides masking/unmasking of interrupts, as well as
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* acknowledging of edge-triggered interrupts.
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*/
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static irqreturn_t spurious_eim_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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printk(KERN_WARNING "Spurious EIM interrupt %d\n", irq);
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disable_irq(irq);
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return IRQ_NONE;
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}
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static struct irqaction eim_spurious_action = {
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.handler = spurious_eim_interrupt,
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};
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static irqreturn_t eim_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct irq_controller * irqc = dev_id;
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struct at32_sm *sm = to_eim(irqc);
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unsigned long pending;
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/*
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* No need to disable interrupts globally. The interrupt
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* level relevant to this group must be masked all the time,
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* so we know that this particular EIM instance will not be
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* re-entered.
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*/
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spin_lock(&sm->lock);
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pending = intc_get_pending(sm->irqc.irq_group);
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if (unlikely(!pending)) {
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printk(KERN_ERR "EIM (group %u): No interrupts pending!\n",
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sm->irqc.irq_group);
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goto unlock;
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}
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do {
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struct irqaction *action;
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unsigned int i;
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i = fls(pending) - 1;
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pending &= ~(1 << i);
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action = sm->action[i];
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/* Acknowledge the interrupt */
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sm_writel(sm, EIM_ICR, 1 << i);
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spin_unlock(&sm->lock);
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if (action->flags & SA_INTERRUPT)
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local_irq_disable();
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action->handler(sm->irqc.first_irq + i, action->dev_id, regs);
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local_irq_enable();
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spin_lock(&sm->lock);
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if (action->flags & SA_SAMPLE_RANDOM)
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add_interrupt_randomness(sm->irqc.first_irq + i);
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} while (pending);
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unlock:
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spin_unlock(&sm->lock);
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return IRQ_HANDLED;
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}
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static void eim_mask(struct irq_controller *irqc, unsigned int irq)
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{
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struct at32_sm *sm = to_eim(irqc);
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unsigned int i;
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i = irq - sm->irqc.first_irq;
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sm_writel(sm, EIM_IDR, 1 << i);
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}
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static void eim_unmask(struct irq_controller *irqc, unsigned int irq)
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{
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struct at32_sm *sm = to_eim(irqc);
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unsigned int i;
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i = irq - sm->irqc.first_irq;
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sm_writel(sm, EIM_IER, 1 << i);
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}
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static int eim_setup(struct irq_controller *irqc, unsigned int irq,
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struct irqaction *action)
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{
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struct at32_sm *sm = to_eim(irqc);
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sm->action[irq - sm->irqc.first_irq] = action;
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/* Acknowledge earlier interrupts */
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sm_writel(sm, EIM_ICR, (1<<(irq - sm->irqc.first_irq)));
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eim_unmask(irqc, irq);
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return 0;
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}
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static void eim_free(struct irq_controller *irqc, unsigned int irq,
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void *dev)
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{
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struct at32_sm *sm = to_eim(irqc);
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eim_mask(irqc, irq);
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sm->action[irq - sm->irqc.first_irq] = &eim_spurious_action;
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}
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static int eim_set_type(struct irq_controller *irqc, unsigned int irq,
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unsigned int type)
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{
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struct at32_sm *sm = to_eim(irqc);
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unsigned long flags;
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u32 value, pattern;
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spin_lock_irqsave(&sm->lock, flags);
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pattern = 1 << (irq - sm->irqc.first_irq);
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value = sm_readl(sm, EIM_MODE);
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if (type & IRQ_TYPE_LEVEL)
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value |= pattern;
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else
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value &= ~pattern;
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sm_writel(sm, EIM_MODE, value);
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value = sm_readl(sm, EIM_EDGE);
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if (type & IRQ_EDGE_RISING)
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value |= pattern;
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else
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value &= ~pattern;
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sm_writel(sm, EIM_EDGE, value);
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value = sm_readl(sm, EIM_LEVEL);
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if (type & IRQ_LEVEL_HIGH)
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value |= pattern;
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else
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value &= ~pattern;
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sm_writel(sm, EIM_LEVEL, value);
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spin_unlock_irqrestore(&sm->lock, flags);
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return 0;
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}
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static unsigned int eim_get_type(struct irq_controller *irqc,
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unsigned int irq)
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{
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struct at32_sm *sm = to_eim(irqc);
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unsigned long flags;
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unsigned int type = 0;
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u32 mode, edge, level, pattern;
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pattern = 1 << (irq - sm->irqc.first_irq);
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spin_lock_irqsave(&sm->lock, flags);
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mode = sm_readl(sm, EIM_MODE);
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edge = sm_readl(sm, EIM_EDGE);
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level = sm_readl(sm, EIM_LEVEL);
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spin_unlock_irqrestore(&sm->lock, flags);
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if (mode & pattern)
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type |= IRQ_TYPE_LEVEL;
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if (edge & pattern)
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type |= IRQ_EDGE_RISING;
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if (level & pattern)
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type |= IRQ_LEVEL_HIGH;
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return type;
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}
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static struct irq_controller_class eim_irq_class = {
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.typename = "EIM",
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.handle = eim_handle_irq,
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.setup = eim_setup,
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.free = eim_free,
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.mask = eim_mask,
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.unmask = eim_unmask,
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.set_type = eim_set_type,
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.get_type = eim_get_type,
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};
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static int __init eim_init(void)
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{
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struct at32_sm *sm = &system_manager;
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unsigned int i;
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u32 pattern;
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int ret;
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/*
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* The EIM is really the same module as SM, so register
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* mapping, etc. has been taken care of already.
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*/
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/*
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* Find out how many interrupt lines that are actually
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* implemented in hardware.
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*/
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sm_writel(sm, EIM_IDR, ~0UL);
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sm_writel(sm, EIM_MODE, ~0UL);
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pattern = sm_readl(sm, EIM_MODE);
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sm->irqc.nr_irqs = fls(pattern);
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ret = -ENOMEM;
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sm->action = kmalloc(sizeof(*sm->action) * sm->irqc.nr_irqs,
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GFP_KERNEL);
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if (!sm->action)
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goto out;
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for (i = 0; i < sm->irqc.nr_irqs; i++)
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sm->action[i] = &eim_spurious_action;
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spin_lock_init(&sm->lock);
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sm->irqc.irq_group = sm->pdev->resource[SM_EIM_IRQ_RESOURCE].start;
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sm->irqc.class = &eim_irq_class;
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ret = intc_register_controller(&sm->irqc);
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if (ret < 0)
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goto out_free_actions;
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printk("EIM: External Interrupt Module at 0x%p, IRQ group %u\n",
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sm->regs, sm->irqc.irq_group);
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printk("EIM: Handling %u external IRQs, starting with IRQ%u\n",
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sm->irqc.nr_irqs, sm->irqc.first_irq);
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return 0;
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out_free_actions:
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kfree(sm->action);
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out:
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return ret;
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}
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arch_initcall(eim_init);
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