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MT8192 contains an experimental Accelerator Coherency Port implementation, which does not work correctly but was unintentionally enabled by default. For correct operation of the GPU, we must set a chicken bit disabling ACP on MT8192. Adapted from the following downstream change to the out-of-tree, legacy Mali GPU driver: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5 Note this change is required for both Panfrost and the legacy kernel driver. Co-developed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Cc: Nick Fan <Nick.Fan@mediatek.com> Cc: Nicolas Boichat <drinkcat@chromium.org> Cc: Chen-Yu Tsai <wenst@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
93 lines
2.8 KiB
C
93 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
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*/
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#include <linux/export.h>
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#include <linux/jiffies.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/soc/mediatek/infracfg.h>
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#include <asm/processor.h>
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#define MTK_POLL_DELAY_US 10
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#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
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/**
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* mtk_infracfg_set_bus_protection - enable bus protection
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* @infracfg: The infracfg regmap
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* @mask: The mask containing the protection bits to be enabled.
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* @reg_update: The boolean flag determines to set the protection bits
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* by regmap_update_bits with enable register(PROTECTEN) or
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* by regmap_write with set register(PROTECTEN_SET).
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*
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* This function enables the bus protection bits for disabled power
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* domains so that the system does not hang when some unit accesses the
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* bus while in power down.
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*/
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int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
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bool reg_update)
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{
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u32 val;
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int ret;
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if (reg_update)
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regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
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mask);
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else
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regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
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ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
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val, (val & mask) == mask,
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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return ret;
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}
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/**
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* mtk_infracfg_clear_bus_protection - disable bus protection
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* @infracfg: The infracfg regmap
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* @mask: The mask containing the protection bits to be disabled.
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* @reg_update: The boolean flag determines to clear the protection bits
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* by regmap_update_bits with enable register(PROTECTEN) or
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* by regmap_write with clear register(PROTECTEN_CLR).
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*
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* This function disables the bus protection bits previously enabled with
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* mtk_infracfg_set_bus_protection.
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*/
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int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
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bool reg_update)
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{
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int ret;
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u32 val;
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if (reg_update)
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regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
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else
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regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
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ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
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val, !(val & mask),
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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return ret;
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}
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static int __init mtk_infracfg_init(void)
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{
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struct regmap *infracfg;
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/*
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* MT8192 has an experimental path to route GPU traffic to the DSU's
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* Accelerator Coherency Port, which is inadvertently enabled by
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* default. It turns out not to work, so disable it to prevent spurious
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* GPU faults.
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*/
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infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg");
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if (!IS_ERR(infracfg))
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regmap_set_bits(infracfg, MT8192_INFRA_CTRL,
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MT8192_INFRA_CTRL_DISABLE_MFG2ACP);
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return 0;
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}
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postcore_initcall(mtk_infracfg_init);
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