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![Linus Torvalds](/assets/img/avatar_default.png)
There are minor updates to SoC specific drivers for chips by Rockchip, Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy driver changes include: - Several conversions of DT bindings to yaml format. - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs. - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core), and support for more chips in the RPMh power domains and the soc-id. - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP. - Apple M1 gains support for the on-chip NVMe controller, making it possible to finally use the internal disks. This also includes SoC drivers for their RTKit IPC and for the SART DMA address filter. For other subsystems that merge their drivers through the SoC tree, we have - Firmware drivers for the ARM firmware stack including TEE, OP-TEE, SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE now has a cache for firmware argument structures as an optimization, and SCMI now supports the 3.1 version of the specification. - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers - Memory controller updates for Tegra, and a few updates for other platforms. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKOXOoACgkQmmx57+YA GNlpVQ//eQGfL0WktE5G/y0mCVuVHtXT5nSjHMgjTOdb9+QvaATCfxnLXvP7Gq7C 7YzJd68G+2ZC4rUkkjTxyMICT7eIrJSAIAFn4PWee4EQ5DfbHgG+1tToTjxqb+QQ 6wGB5MVaYUhjZE30kY2E8a+OKxHtEnkt9wcch6ei0vzsMZquQJF6byfHd5+I4Knd CyDmXX8ZGXK3FnhvuBLr3Rgwyhs0X4Ju7UaONLZxBYxdnh8WmymRszmMnv5qEkub KDe8fbhFamOT3Z55JdCA5xq7LvUzjsKpTGFxFcS0ptbkTmtAsuyYqqiWvAPx3D5u 5TxVGSx9QKid6fpIsITZ2ptO6fgljh1W9b/3Y3/eltudXsM1qqSxyN2Hre+M9egf WEDADqbNR5Y5+bq1iZWI348jXkNHVPpsLHI9Ihqf4yyrKwFkmRmNLnws53XTAPH2 FPXZvJjwFDBDHGfewSoLFePXUPNytVLXbr6Mq72ZyTDIBDU8Mxh666Wd8bu4tgbG 1Y2pMjDIdXDOsljM6Of5D3XjM1kuDwEmFxWGy+cKLgoEbHLeE1xIbTjUir4687+d VNHdtsIRFPRZzz2lUSmI8vlA2aewMWrkOF/Ulz8xh6gG8uitMSfOxghg4IWOfRVM mlvgFP5eqTInmQcbWRxaRO9JzP+rPp1sAcEpsBmuEHw5Akflbc8= =XoLF -----END PGP SIGNATURE----- Merge tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "There are minor updates to SoC specific drivers for chips by Rockchip, Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy driver changes include: - Several conversions of DT bindings to yaml format. - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs. - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core), and support for more chips in the RPMh power domains and the soc-id. - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP. - Apple M1 gains support for the on-chip NVMe controller, making it possible to finally use the internal disks. This also includes SoC drivers for their RTKit IPC and for the SART DMA address filter. For other subsystems that merge their drivers through the SoC tree, we have - Firmware drivers for the ARM firmware stack including TEE, OP-TEE, SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE now has a cache for firmware argument structures as an optimization, and SCMI now supports the 3.1 version of the specification. - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers - Memory controller updates for Tegra, and a few updates for other platforms" * tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits) memory: tegra: Add MC error logging on Tegra186 onward memory: tegra: Add memory controller channels support memory: tegra: Add APE memory clients for Tegra234 memory: tegra: Add Tegra234 support nvme-apple: fix sparse endianess warnings soc/tegra: pmc: Document core domain fields soc: qcom: pdr: use static for servreg_* variables soc: imx: fix semicolon.cocci warnings soc: renesas: R-Car V3U is R-Car Gen4 soc: imx: add i.MX8MP HDMI blk-ctrl soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl soc: imx: add i.MX8MP HSIO blk-ctrl soc: imx: imx8m-blk-ctrl: set power device name soc: qcom: llcc: Add sc8180x and sc8280xp configurations dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles soc/tegra: pmc: Select REGMAP dt-bindings: reset: st,sti-powerdown: Convert to yaml dt-bindings: reset: st,sti-picophyreset: Convert to yaml dt-bindings: reset: socfpga: Convert to yaml dt-bindings: reset: snps,axs10x-reset: Convert to yaml ...
1201 lines
34 KiB
C
1201 lines
34 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip Generic power domain support.
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*
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* Copyright (c) 2015 ROCKCHIP, Co. Ltd.
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*/
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/err.h>
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#include <linux/mutex.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/of_address.h>
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#include <linux/of_clk.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <soc/rockchip/pm_domains.h>
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#include <dt-bindings/power/px30-power.h>
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#include <dt-bindings/power/rk3036-power.h>
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#include <dt-bindings/power/rk3066-power.h>
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#include <dt-bindings/power/rk3128-power.h>
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#include <dt-bindings/power/rk3188-power.h>
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#include <dt-bindings/power/rk3228-power.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include <dt-bindings/power/rk3328-power.h>
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#include <dt-bindings/power/rk3366-power.h>
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#include <dt-bindings/power/rk3368-power.h>
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#include <dt-bindings/power/rk3399-power.h>
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#include <dt-bindings/power/rk3568-power.h>
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struct rockchip_domain_info {
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const char *name;
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int pwr_mask;
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int status_mask;
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int req_mask;
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int idle_mask;
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int ack_mask;
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bool active_wakeup;
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int pwr_w_mask;
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int req_w_mask;
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};
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struct rockchip_pmu_info {
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u32 pwr_offset;
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u32 status_offset;
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u32 req_offset;
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u32 idle_offset;
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u32 ack_offset;
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u32 core_pwrcnt_offset;
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u32 gpu_pwrcnt_offset;
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unsigned int core_power_transition_time;
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unsigned int gpu_power_transition_time;
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int num_domains;
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const struct rockchip_domain_info *domain_info;
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};
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#define MAX_QOS_REGS_NUM 5
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#define QOS_PRIORITY 0x08
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#define QOS_MODE 0x0c
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#define QOS_BANDWIDTH 0x10
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#define QOS_SATURATION 0x14
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#define QOS_EXTCONTROL 0x18
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struct rockchip_pm_domain {
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struct generic_pm_domain genpd;
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const struct rockchip_domain_info *info;
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struct rockchip_pmu *pmu;
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int num_qos;
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struct regmap **qos_regmap;
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u32 *qos_save_regs[MAX_QOS_REGS_NUM];
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int num_clks;
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struct clk_bulk_data *clks;
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};
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struct rockchip_pmu {
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struct device *dev;
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struct regmap *regmap;
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const struct rockchip_pmu_info *info;
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struct mutex mutex; /* mutex lock for pmu */
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struct genpd_onecell_data genpd_data;
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struct generic_pm_domain *domains[];
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};
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#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
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#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
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{ \
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.name = _name, \
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.pwr_mask = (pwr), \
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.status_mask = (status), \
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.req_mask = (req), \
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.idle_mask = (idle), \
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.ack_mask = (ack), \
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.active_wakeup = (wakeup), \
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}
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#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
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{ \
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.name = _name, \
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.pwr_w_mask = (pwr) << 16, \
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.pwr_mask = (pwr), \
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.status_mask = (status), \
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.req_w_mask = (req) << 16, \
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.req_mask = (req), \
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.idle_mask = (idle), \
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.ack_mask = (ack), \
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.active_wakeup = wakeup, \
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}
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#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
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{ \
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.name = _name, \
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.req_mask = (req), \
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.req_w_mask = (req) << 16, \
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.ack_mask = (ack), \
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.idle_mask = (idle), \
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.active_wakeup = wakeup, \
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}
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#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
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DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
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#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
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DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
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#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
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DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
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#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
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DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
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#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
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DOMAIN(name, pwr, status, req, req, req, wakeup)
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#define DOMAIN_RK3568(name, pwr, req, wakeup) \
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DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
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/*
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* Dynamic Memory Controller may need to coordinate with us -- see
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* rockchip_pmu_block().
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*
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* dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
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* block() while we're initializing the PMU.
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*/
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static DEFINE_MUTEX(dmc_pmu_mutex);
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static struct rockchip_pmu *dmc_pmu;
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/*
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* Block PMU transitions and make sure they don't interfere with ARM Trusted
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* Firmware operations. There are two conflicts, noted in the comments below.
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*
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* Caller must unblock PMU transitions via rockchip_pmu_unblock().
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*/
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int rockchip_pmu_block(void)
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{
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struct rockchip_pmu *pmu;
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struct generic_pm_domain *genpd;
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struct rockchip_pm_domain *pd;
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int i, ret;
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mutex_lock(&dmc_pmu_mutex);
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/* No PMU (yet)? Then we just block rockchip_pmu_probe(). */
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if (!dmc_pmu)
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return 0;
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pmu = dmc_pmu;
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/*
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* mutex blocks all idle transitions: we can't touch the
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* PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted
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* Firmware might be using it.
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*/
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mutex_lock(&pmu->mutex);
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/*
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* Power domain clocks: Per Rockchip, we *must* keep certain clocks
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* enabled for the duration of power-domain transitions. Most
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* transitions are handled by this driver, but some cases (in
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* particular, DRAM DVFS / memory-controller idle) must be handled by
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* firmware. Firmware can handle most clock management via a special
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* "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this
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* doesn't handle PLLs. We can assist this transition by doing the
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* clock management on behalf of firmware.
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*/
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for (i = 0; i < pmu->genpd_data.num_domains; i++) {
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genpd = pmu->genpd_data.domains[i];
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if (genpd) {
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pd = to_rockchip_pd(genpd);
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ret = clk_bulk_enable(pd->num_clks, pd->clks);
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if (ret < 0) {
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dev_err(pmu->dev,
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"failed to enable clks for domain '%s': %d\n",
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genpd->name, ret);
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goto err;
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}
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}
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}
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return 0;
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err:
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for (i = i - 1; i >= 0; i--) {
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genpd = pmu->genpd_data.domains[i];
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if (genpd) {
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pd = to_rockchip_pd(genpd);
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clk_bulk_disable(pd->num_clks, pd->clks);
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}
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}
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mutex_unlock(&pmu->mutex);
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mutex_unlock(&dmc_pmu_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(rockchip_pmu_block);
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/* Unblock PMU transitions. */
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void rockchip_pmu_unblock(void)
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{
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struct rockchip_pmu *pmu;
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struct generic_pm_domain *genpd;
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struct rockchip_pm_domain *pd;
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int i;
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if (dmc_pmu) {
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pmu = dmc_pmu;
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for (i = 0; i < pmu->genpd_data.num_domains; i++) {
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genpd = pmu->genpd_data.domains[i];
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if (genpd) {
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pd = to_rockchip_pd(genpd);
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clk_bulk_disable(pd->num_clks, pd->clks);
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}
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}
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mutex_unlock(&pmu->mutex);
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}
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mutex_unlock(&dmc_pmu_mutex);
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}
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EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
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static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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const struct rockchip_domain_info *pd_info = pd->info;
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unsigned int val;
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regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
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return (val & pd_info->idle_mask) == pd_info->idle_mask;
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}
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static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
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{
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unsigned int val;
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regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
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return val;
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}
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static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
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bool idle)
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{
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const struct rockchip_domain_info *pd_info = pd->info;
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struct generic_pm_domain *genpd = &pd->genpd;
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struct rockchip_pmu *pmu = pd->pmu;
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unsigned int target_ack;
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unsigned int val;
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bool is_idle;
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int ret;
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if (pd_info->req_mask == 0)
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return 0;
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else if (pd_info->req_w_mask)
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regmap_write(pmu->regmap, pmu->info->req_offset,
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idle ? (pd_info->req_mask | pd_info->req_w_mask) :
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pd_info->req_w_mask);
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else
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regmap_update_bits(pmu->regmap, pmu->info->req_offset,
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pd_info->req_mask, idle ? -1U : 0);
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wmb();
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/* Wait util idle_ack = 1 */
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target_ack = idle ? pd_info->ack_mask : 0;
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ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
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(val & pd_info->ack_mask) == target_ack,
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0, 10000);
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if (ret) {
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dev_err(pmu->dev,
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"failed to get ack on domain '%s', val=0x%x\n",
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genpd->name, val);
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return ret;
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}
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ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
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is_idle, is_idle == idle, 0, 10000);
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if (ret) {
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dev_err(pmu->dev,
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"failed to set idle on domain '%s', val=%d\n",
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genpd->name, is_idle);
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return ret;
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}
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return 0;
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}
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static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
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{
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int i;
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for (i = 0; i < pd->num_qos; i++) {
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regmap_read(pd->qos_regmap[i],
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QOS_PRIORITY,
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&pd->qos_save_regs[0][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_MODE,
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&pd->qos_save_regs[1][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_BANDWIDTH,
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&pd->qos_save_regs[2][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_SATURATION,
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&pd->qos_save_regs[3][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_EXTCONTROL,
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&pd->qos_save_regs[4][i]);
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}
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return 0;
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}
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static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
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{
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int i;
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for (i = 0; i < pd->num_qos; i++) {
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regmap_write(pd->qos_regmap[i],
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QOS_PRIORITY,
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pd->qos_save_regs[0][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_MODE,
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pd->qos_save_regs[1][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_BANDWIDTH,
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pd->qos_save_regs[2][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_SATURATION,
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pd->qos_save_regs[3][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_EXTCONTROL,
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pd->qos_save_regs[4][i]);
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}
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return 0;
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}
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static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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unsigned int val;
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/* check idle status for idle-only domains */
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if (pd->info->status_mask == 0)
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return !rockchip_pmu_domain_is_idle(pd);
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regmap_read(pmu->regmap, pmu->info->status_offset, &val);
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/* 1'b0: power on, 1'b1: power off */
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return !(val & pd->info->status_mask);
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}
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static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
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bool on)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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struct generic_pm_domain *genpd = &pd->genpd;
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bool is_on;
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if (pd->info->pwr_mask == 0)
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return;
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else if (pd->info->pwr_w_mask)
|
|
regmap_write(pmu->regmap, pmu->info->pwr_offset,
|
|
on ? pd->info->pwr_w_mask :
|
|
(pd->info->pwr_mask | pd->info->pwr_w_mask));
|
|
else
|
|
regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
|
|
pd->info->pwr_mask, on ? 0 : -1U);
|
|
|
|
wmb();
|
|
|
|
if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
|
|
is_on == on, 0, 10000)) {
|
|
dev_err(pmu->dev,
|
|
"failed to set domain '%s', val=%d\n",
|
|
genpd->name, is_on);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
|
|
{
|
|
struct rockchip_pmu *pmu = pd->pmu;
|
|
int ret;
|
|
|
|
mutex_lock(&pmu->mutex);
|
|
|
|
if (rockchip_pmu_domain_is_on(pd) != power_on) {
|
|
ret = clk_bulk_enable(pd->num_clks, pd->clks);
|
|
if (ret < 0) {
|
|
dev_err(pmu->dev, "failed to enable clocks\n");
|
|
mutex_unlock(&pmu->mutex);
|
|
return ret;
|
|
}
|
|
|
|
if (!power_on) {
|
|
rockchip_pmu_save_qos(pd);
|
|
|
|
/* if powering down, idle request to NIU first */
|
|
rockchip_pmu_set_idle_request(pd, true);
|
|
}
|
|
|
|
rockchip_do_pmu_set_power_domain(pd, power_on);
|
|
|
|
if (power_on) {
|
|
/* if powering up, leave idle mode */
|
|
rockchip_pmu_set_idle_request(pd, false);
|
|
|
|
rockchip_pmu_restore_qos(pd);
|
|
}
|
|
|
|
clk_bulk_disable(pd->num_clks, pd->clks);
|
|
}
|
|
|
|
mutex_unlock(&pmu->mutex);
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_pd_power_on(struct generic_pm_domain *domain)
|
|
{
|
|
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
|
|
|
|
return rockchip_pd_power(pd, true);
|
|
}
|
|
|
|
static int rockchip_pd_power_off(struct generic_pm_domain *domain)
|
|
{
|
|
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
|
|
|
|
return rockchip_pd_power(pd, false);
|
|
}
|
|
|
|
static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
|
|
struct device *dev)
|
|
{
|
|
struct clk *clk;
|
|
int i;
|
|
int error;
|
|
|
|
dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
|
|
|
|
error = pm_clk_create(dev);
|
|
if (error) {
|
|
dev_err(dev, "pm_clk_create failed %d\n", error);
|
|
return error;
|
|
}
|
|
|
|
i = 0;
|
|
while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
|
|
dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
|
|
error = pm_clk_add_clk(dev, clk);
|
|
if (error) {
|
|
dev_err(dev, "pm_clk_add_clk failed %d\n", error);
|
|
clk_put(clk);
|
|
pm_clk_destroy(dev);
|
|
return error;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
|
|
struct device *dev)
|
|
{
|
|
dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
|
|
|
|
pm_clk_destroy(dev);
|
|
}
|
|
|
|
static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
|
|
struct device_node *node)
|
|
{
|
|
const struct rockchip_domain_info *pd_info;
|
|
struct rockchip_pm_domain *pd;
|
|
struct device_node *qos_node;
|
|
int i, j;
|
|
u32 id;
|
|
int error;
|
|
|
|
error = of_property_read_u32(node, "reg", &id);
|
|
if (error) {
|
|
dev_err(pmu->dev,
|
|
"%pOFn: failed to retrieve domain id (reg): %d\n",
|
|
node, error);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (id >= pmu->info->num_domains) {
|
|
dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
|
|
node, id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pd_info = &pmu->info->domain_info[id];
|
|
if (!pd_info) {
|
|
dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
|
|
node, id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
|
|
if (!pd)
|
|
return -ENOMEM;
|
|
|
|
pd->info = pd_info;
|
|
pd->pmu = pmu;
|
|
|
|
pd->num_clks = of_clk_get_parent_count(node);
|
|
if (pd->num_clks > 0) {
|
|
pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
|
|
sizeof(*pd->clks), GFP_KERNEL);
|
|
if (!pd->clks)
|
|
return -ENOMEM;
|
|
} else {
|
|
dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
|
|
node, pd->num_clks);
|
|
pd->num_clks = 0;
|
|
}
|
|
|
|
for (i = 0; i < pd->num_clks; i++) {
|
|
pd->clks[i].clk = of_clk_get(node, i);
|
|
if (IS_ERR(pd->clks[i].clk)) {
|
|
error = PTR_ERR(pd->clks[i].clk);
|
|
dev_err(pmu->dev,
|
|
"%pOFn: failed to get clk at index %d: %d\n",
|
|
node, i, error);
|
|
return error;
|
|
}
|
|
}
|
|
|
|
error = clk_bulk_prepare(pd->num_clks, pd->clks);
|
|
if (error)
|
|
goto err_put_clocks;
|
|
|
|
pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
|
|
NULL);
|
|
|
|
if (pd->num_qos > 0) {
|
|
pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
|
|
sizeof(*pd->qos_regmap),
|
|
GFP_KERNEL);
|
|
if (!pd->qos_regmap) {
|
|
error = -ENOMEM;
|
|
goto err_unprepare_clocks;
|
|
}
|
|
|
|
for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
|
|
pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
|
|
pd->num_qos,
|
|
sizeof(u32),
|
|
GFP_KERNEL);
|
|
if (!pd->qos_save_regs[j]) {
|
|
error = -ENOMEM;
|
|
goto err_unprepare_clocks;
|
|
}
|
|
}
|
|
|
|
for (j = 0; j < pd->num_qos; j++) {
|
|
qos_node = of_parse_phandle(node, "pm_qos", j);
|
|
if (!qos_node) {
|
|
error = -ENODEV;
|
|
goto err_unprepare_clocks;
|
|
}
|
|
pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
|
|
if (IS_ERR(pd->qos_regmap[j])) {
|
|
error = -ENODEV;
|
|
of_node_put(qos_node);
|
|
goto err_unprepare_clocks;
|
|
}
|
|
of_node_put(qos_node);
|
|
}
|
|
}
|
|
|
|
error = rockchip_pd_power(pd, true);
|
|
if (error) {
|
|
dev_err(pmu->dev,
|
|
"failed to power on domain '%pOFn': %d\n",
|
|
node, error);
|
|
goto err_unprepare_clocks;
|
|
}
|
|
|
|
if (pd->info->name)
|
|
pd->genpd.name = pd->info->name;
|
|
else
|
|
pd->genpd.name = kbasename(node->full_name);
|
|
pd->genpd.power_off = rockchip_pd_power_off;
|
|
pd->genpd.power_on = rockchip_pd_power_on;
|
|
pd->genpd.attach_dev = rockchip_pd_attach_dev;
|
|
pd->genpd.detach_dev = rockchip_pd_detach_dev;
|
|
pd->genpd.flags = GENPD_FLAG_PM_CLK;
|
|
if (pd_info->active_wakeup)
|
|
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
|
|
pm_genpd_init(&pd->genpd, NULL, false);
|
|
|
|
pmu->genpd_data.domains[id] = &pd->genpd;
|
|
return 0;
|
|
|
|
err_unprepare_clocks:
|
|
clk_bulk_unprepare(pd->num_clks, pd->clks);
|
|
err_put_clocks:
|
|
clk_bulk_put(pd->num_clks, pd->clks);
|
|
return error;
|
|
}
|
|
|
|
static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
|
|
{
|
|
int ret;
|
|
|
|
/*
|
|
* We're in the error cleanup already, so we only complain,
|
|
* but won't emit another error on top of the original one.
|
|
*/
|
|
ret = pm_genpd_remove(&pd->genpd);
|
|
if (ret < 0)
|
|
dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
|
|
pd->genpd.name, ret);
|
|
|
|
clk_bulk_unprepare(pd->num_clks, pd->clks);
|
|
clk_bulk_put(pd->num_clks, pd->clks);
|
|
|
|
/* protect the zeroing of pm->num_clks */
|
|
mutex_lock(&pd->pmu->mutex);
|
|
pd->num_clks = 0;
|
|
mutex_unlock(&pd->pmu->mutex);
|
|
|
|
/* devm will free our memory */
|
|
}
|
|
|
|
static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
|
|
{
|
|
struct generic_pm_domain *genpd;
|
|
struct rockchip_pm_domain *pd;
|
|
int i;
|
|
|
|
for (i = 0; i < pmu->genpd_data.num_domains; i++) {
|
|
genpd = pmu->genpd_data.domains[i];
|
|
if (genpd) {
|
|
pd = to_rockchip_pd(genpd);
|
|
rockchip_pm_remove_one_domain(pd);
|
|
}
|
|
}
|
|
|
|
/* devm will free our memory */
|
|
}
|
|
|
|
static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
|
|
u32 domain_reg_offset,
|
|
unsigned int count)
|
|
{
|
|
/* First configure domain power down transition count ... */
|
|
regmap_write(pmu->regmap, domain_reg_offset, count);
|
|
/* ... and then power up count. */
|
|
regmap_write(pmu->regmap, domain_reg_offset + 4, count);
|
|
}
|
|
|
|
static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
|
|
struct device_node *parent)
|
|
{
|
|
struct device_node *np;
|
|
struct generic_pm_domain *child_domain, *parent_domain;
|
|
int error;
|
|
|
|
for_each_child_of_node(parent, np) {
|
|
u32 idx;
|
|
|
|
error = of_property_read_u32(parent, "reg", &idx);
|
|
if (error) {
|
|
dev_err(pmu->dev,
|
|
"%pOFn: failed to retrieve domain id (reg): %d\n",
|
|
parent, error);
|
|
goto err_out;
|
|
}
|
|
parent_domain = pmu->genpd_data.domains[idx];
|
|
|
|
error = rockchip_pm_add_one_domain(pmu, np);
|
|
if (error) {
|
|
dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
|
|
np, error);
|
|
goto err_out;
|
|
}
|
|
|
|
error = of_property_read_u32(np, "reg", &idx);
|
|
if (error) {
|
|
dev_err(pmu->dev,
|
|
"%pOFn: failed to retrieve domain id (reg): %d\n",
|
|
np, error);
|
|
goto err_out;
|
|
}
|
|
child_domain = pmu->genpd_data.domains[idx];
|
|
|
|
error = pm_genpd_add_subdomain(parent_domain, child_domain);
|
|
if (error) {
|
|
dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
|
|
parent_domain->name, child_domain->name, error);
|
|
goto err_out;
|
|
} else {
|
|
dev_dbg(pmu->dev, "%s add subdomain: %s\n",
|
|
parent_domain->name, child_domain->name);
|
|
}
|
|
|
|
rockchip_pm_add_subdomain(pmu, np);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
of_node_put(np);
|
|
return error;
|
|
}
|
|
|
|
static int rockchip_pm_domain_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct device_node *node;
|
|
struct device *parent;
|
|
struct rockchip_pmu *pmu;
|
|
const struct of_device_id *match;
|
|
const struct rockchip_pmu_info *pmu_info;
|
|
int error;
|
|
|
|
if (!np) {
|
|
dev_err(dev, "device tree node not found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
match = of_match_device(dev->driver->of_match_table, dev);
|
|
if (!match || !match->data) {
|
|
dev_err(dev, "missing pmu data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pmu_info = match->data;
|
|
|
|
pmu = devm_kzalloc(dev,
|
|
struct_size(pmu, domains, pmu_info->num_domains),
|
|
GFP_KERNEL);
|
|
if (!pmu)
|
|
return -ENOMEM;
|
|
|
|
pmu->dev = &pdev->dev;
|
|
mutex_init(&pmu->mutex);
|
|
|
|
pmu->info = pmu_info;
|
|
|
|
pmu->genpd_data.domains = pmu->domains;
|
|
pmu->genpd_data.num_domains = pmu_info->num_domains;
|
|
|
|
parent = dev->parent;
|
|
if (!parent) {
|
|
dev_err(dev, "no parent for syscon devices\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pmu->regmap = syscon_node_to_regmap(parent->of_node);
|
|
if (IS_ERR(pmu->regmap)) {
|
|
dev_err(dev, "no regmap available\n");
|
|
return PTR_ERR(pmu->regmap);
|
|
}
|
|
|
|
/*
|
|
* Configure power up and down transition delays for CORE
|
|
* and GPU domains.
|
|
*/
|
|
if (pmu_info->core_power_transition_time)
|
|
rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
|
|
pmu_info->core_power_transition_time);
|
|
if (pmu_info->gpu_pwrcnt_offset)
|
|
rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
|
|
pmu_info->gpu_power_transition_time);
|
|
|
|
error = -ENODEV;
|
|
|
|
/*
|
|
* Prevent any rockchip_pmu_block() from racing with the remainder of
|
|
* setup (clocks, register initialization).
|
|
*/
|
|
mutex_lock(&dmc_pmu_mutex);
|
|
|
|
for_each_available_child_of_node(np, node) {
|
|
error = rockchip_pm_add_one_domain(pmu, node);
|
|
if (error) {
|
|
dev_err(dev, "failed to handle node %pOFn: %d\n",
|
|
node, error);
|
|
of_node_put(node);
|
|
goto err_out;
|
|
}
|
|
|
|
error = rockchip_pm_add_subdomain(pmu, node);
|
|
if (error < 0) {
|
|
dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
|
|
node, error);
|
|
of_node_put(node);
|
|
goto err_out;
|
|
}
|
|
}
|
|
|
|
if (error) {
|
|
dev_dbg(dev, "no power domains defined\n");
|
|
goto err_out;
|
|
}
|
|
|
|
error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
|
|
if (error) {
|
|
dev_err(dev, "failed to add provider: %d\n", error);
|
|
goto err_out;
|
|
}
|
|
|
|
/* We only expect one PMU. */
|
|
if (!WARN_ON_ONCE(dmc_pmu))
|
|
dmc_pmu = pmu;
|
|
|
|
mutex_unlock(&dmc_pmu_mutex);
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
rockchip_pm_domain_cleanup(pmu);
|
|
mutex_unlock(&dmc_pmu_mutex);
|
|
return error;
|
|
}
|
|
|
|
static const struct rockchip_domain_info px30_pm_domains[] = {
|
|
[PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
|
|
[PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
|
|
[PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
|
|
[PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
|
|
[PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
|
|
[PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
|
|
[PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
|
|
[PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3036_pm_domains[] = {
|
|
[RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
|
|
[RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
|
|
[RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
|
|
[RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
|
|
[RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
|
|
[RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
|
|
[RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3066_pm_domains[] = {
|
|
[RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
|
|
[RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
|
|
[RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
|
|
[RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
|
|
[RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3128_pm_domains[] = {
|
|
[RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
|
|
[RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
|
|
[RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
|
|
[RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
|
|
[RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3188_pm_domains[] = {
|
|
[RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
|
|
[RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
|
|
[RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
|
|
[RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
|
|
[RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3228_pm_domains[] = {
|
|
[RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
|
|
[RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
|
|
[RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
|
|
[RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
|
|
[RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
|
|
[RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
|
|
[RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
|
|
[RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
|
|
[RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
|
|
[RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
|
|
[RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3288_pm_domains[] = {
|
|
[RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
|
|
[RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
|
|
[RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
|
|
[RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3328_pm_domains[] = {
|
|
[RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
|
|
[RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
|
|
[RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
|
|
[RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
|
|
[RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
|
|
[RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
|
|
[RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
|
|
[RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
|
|
[RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3366_pm_domains[] = {
|
|
[RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
|
|
[RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
|
|
[RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
|
|
[RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
|
|
[RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
|
|
[RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
|
|
[RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3368_pm_domains[] = {
|
|
[RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
|
|
[RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
|
|
[RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
|
|
[RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
|
|
[RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3399_pm_domains[] = {
|
|
[RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
|
|
[RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
|
|
[RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
|
|
[RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
|
|
[RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
|
|
[RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
|
|
[RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
|
|
[RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
|
|
[RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
|
|
[RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
|
|
[RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
|
|
[RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
|
|
[RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
|
|
[RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
|
|
[RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
|
|
[RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
|
|
[RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
|
|
[RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
|
|
[RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
|
|
[RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
|
|
[RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
|
|
[RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
|
|
[RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
|
|
[RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
|
|
[RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
|
|
[RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
|
|
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3568_pm_domains[] = {
|
|
[RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
|
|
[RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
|
|
[RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
|
|
[RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
|
|
[RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
|
|
[RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
|
|
[RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
|
|
[RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
|
|
[RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
|
|
};
|
|
|
|
static const struct rockchip_pmu_info px30_pmu = {
|
|
.pwr_offset = 0x18,
|
|
.status_offset = 0x20,
|
|
.req_offset = 0x64,
|
|
.idle_offset = 0x6c,
|
|
.ack_offset = 0x6c,
|
|
|
|
.num_domains = ARRAY_SIZE(px30_pm_domains),
|
|
.domain_info = px30_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3036_pmu = {
|
|
.req_offset = 0x148,
|
|
.idle_offset = 0x14c,
|
|
.ack_offset = 0x14c,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3036_pm_domains),
|
|
.domain_info = rk3036_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3066_pmu = {
|
|
.pwr_offset = 0x08,
|
|
.status_offset = 0x0c,
|
|
.req_offset = 0x38, /* PMU_MISC_CON1 */
|
|
.idle_offset = 0x0c,
|
|
.ack_offset = 0x0c,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3066_pm_domains),
|
|
.domain_info = rk3066_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3128_pmu = {
|
|
.pwr_offset = 0x04,
|
|
.status_offset = 0x08,
|
|
.req_offset = 0x0c,
|
|
.idle_offset = 0x10,
|
|
.ack_offset = 0x10,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3128_pm_domains),
|
|
.domain_info = rk3128_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3188_pmu = {
|
|
.pwr_offset = 0x08,
|
|
.status_offset = 0x0c,
|
|
.req_offset = 0x38, /* PMU_MISC_CON1 */
|
|
.idle_offset = 0x0c,
|
|
.ack_offset = 0x0c,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3188_pm_domains),
|
|
.domain_info = rk3188_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3228_pmu = {
|
|
.req_offset = 0x40c,
|
|
.idle_offset = 0x488,
|
|
.ack_offset = 0x488,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3228_pm_domains),
|
|
.domain_info = rk3228_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3288_pmu = {
|
|
.pwr_offset = 0x08,
|
|
.status_offset = 0x0c,
|
|
.req_offset = 0x10,
|
|
.idle_offset = 0x14,
|
|
.ack_offset = 0x14,
|
|
|
|
.core_pwrcnt_offset = 0x34,
|
|
.gpu_pwrcnt_offset = 0x3c,
|
|
|
|
.core_power_transition_time = 24, /* 1us */
|
|
.gpu_power_transition_time = 24, /* 1us */
|
|
|
|
.num_domains = ARRAY_SIZE(rk3288_pm_domains),
|
|
.domain_info = rk3288_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3328_pmu = {
|
|
.req_offset = 0x414,
|
|
.idle_offset = 0x484,
|
|
.ack_offset = 0x484,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3328_pm_domains),
|
|
.domain_info = rk3328_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3366_pmu = {
|
|
.pwr_offset = 0x0c,
|
|
.status_offset = 0x10,
|
|
.req_offset = 0x3c,
|
|
.idle_offset = 0x40,
|
|
.ack_offset = 0x40,
|
|
|
|
.core_pwrcnt_offset = 0x48,
|
|
.gpu_pwrcnt_offset = 0x50,
|
|
|
|
.core_power_transition_time = 24,
|
|
.gpu_power_transition_time = 24,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3366_pm_domains),
|
|
.domain_info = rk3366_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3368_pmu = {
|
|
.pwr_offset = 0x0c,
|
|
.status_offset = 0x10,
|
|
.req_offset = 0x3c,
|
|
.idle_offset = 0x40,
|
|
.ack_offset = 0x40,
|
|
|
|
.core_pwrcnt_offset = 0x48,
|
|
.gpu_pwrcnt_offset = 0x50,
|
|
|
|
.core_power_transition_time = 24,
|
|
.gpu_power_transition_time = 24,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3368_pm_domains),
|
|
.domain_info = rk3368_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3399_pmu = {
|
|
.pwr_offset = 0x14,
|
|
.status_offset = 0x18,
|
|
.req_offset = 0x60,
|
|
.idle_offset = 0x64,
|
|
.ack_offset = 0x68,
|
|
|
|
/* ARM Trusted Firmware manages power transition times */
|
|
|
|
.num_domains = ARRAY_SIZE(rk3399_pm_domains),
|
|
.domain_info = rk3399_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3568_pmu = {
|
|
.pwr_offset = 0xa0,
|
|
.status_offset = 0x98,
|
|
.req_offset = 0x50,
|
|
.idle_offset = 0x68,
|
|
.ack_offset = 0x60,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3568_pm_domains),
|
|
.domain_info = rk3568_pm_domains,
|
|
};
|
|
|
|
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
|
|
{
|
|
.compatible = "rockchip,px30-power-controller",
|
|
.data = (void *)&px30_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3036-power-controller",
|
|
.data = (void *)&rk3036_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3066-power-controller",
|
|
.data = (void *)&rk3066_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3128-power-controller",
|
|
.data = (void *)&rk3128_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3188-power-controller",
|
|
.data = (void *)&rk3188_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3228-power-controller",
|
|
.data = (void *)&rk3228_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3288-power-controller",
|
|
.data = (void *)&rk3288_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3328-power-controller",
|
|
.data = (void *)&rk3328_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3366-power-controller",
|
|
.data = (void *)&rk3366_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3368-power-controller",
|
|
.data = (void *)&rk3368_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3399-power-controller",
|
|
.data = (void *)&rk3399_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3568-power-controller",
|
|
.data = (void *)&rk3568_pmu,
|
|
},
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static struct platform_driver rockchip_pm_domain_driver = {
|
|
.probe = rockchip_pm_domain_probe,
|
|
.driver = {
|
|
.name = "rockchip-pm-domain",
|
|
.of_match_table = rockchip_pm_domain_dt_match,
|
|
/*
|
|
* We can't forcibly eject devices from the power
|
|
* domain, so we can't really remove power domains
|
|
* once they were added.
|
|
*/
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
|
|
static int __init rockchip_pm_domain_drv_register(void)
|
|
{
|
|
return platform_driver_register(&rockchip_pm_domain_driver);
|
|
}
|
|
postcore_initcall(rockchip_pm_domain_drv_register);
|