Alibek Omarov 7618133eda clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz ... [ Upstream commit dafebd0f9a ] PLL rate on RK356x is calculated through the simple formula: ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2) The PLL rate setting for 78.75MHz seems to be copied from 96MHz so this patch fixes it and configures it properly. Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com> Fixes: 842f4cb726 ("clk: rockchip: Add more PLL rates for rk3568") Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20230614134750.1056293-1-a1ba.omarov@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <sashal@kernel.org>		2023-09-13 09:42:45 +02:00
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clk-cpu.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-ddr.c	clk: rockchip: Export rockchip_clk_register_ddrclk()	2020-09-22 15:16:37 +02:00
clk-half-divider.c	clk: rockchip: Demote non-conformant kernel-doc header in half-divider	2021-01-26 00:24:05 +01:00
clk-inverter.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
clk-mmc-phase.c	clk: rockchip: fix mmc get phase	2020-03-06 12:06:01 -08:00
clk-muxgrf.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282	2019-06-05 17:36:37 +02:00
clk-pll.c	clk: rockchip: Fix memory leak in rockchip_clk_register_pll()	2022-12-31 13:32:15 +01:00
clk-px30.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3036.c	clk: rockchip: Add support for hclk_sfc on rk3036	2021-07-16 00:33:42 +02:00
clk-rk3128.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3188.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3228.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3288.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3308.c	clk: rockchip: make rk3308 ddrphy4x clock critical	2021-07-29 12:43:11 +02:00
clk-rk3328.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3368.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3399.c	clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent	2023-05-11 23:03:40 +09:00
clk-rk3568.c	clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz	2023-09-13 09:42:45 +02:00
clk-rv1108.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rv1126.c	clk: rockchip: Add clock controller support for RV1126 SoC	2022-09-23 11:15:30 +02:00
clk.c	clk: rockchip: Add MUXTBL variant	2022-09-13 12:09:14 +02:00
clk.h	clk: rockchip: Add clock controller support for RV1126 SoC	2022-09-23 11:15:30 +02:00
Kconfig	clk: rockchip: Add clock controller support for RV1126 SoC	2022-09-23 11:15:30 +02:00
Makefile	clk: rockchip: Add clock controller support for RV1126 SoC	2022-09-23 11:15:30 +02:00
softrst.c	clk: rockchip: Export rockchip_register_softrst()	2020-09-22 15:16:38 +02:00