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![Viresh Kumar](/assets/img/avatar_default.png)
Sometimes boot loaders set CPU frequency to a value outside of frequency table present with cpufreq core. In such cases CPU might be unstable if it has to run on that frequency for long duration of time and so its better to set it to a frequency which is specified in frequency table. On some systems we can't really say what frequency we're running at the moment and so for these we shouldn't check if we are running at a frequency present in frequency table. And so we really can't force this for all the cpufreq drivers. Hence we are created another flag here: CPUFREQ_NEED_INITIAL_FREQ_CHECK that will be marked by platforms which want to go for this check at boot time. Initially this is done for all ARM platforms but others may follow if required. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
374 lines
8.9 KiB
C
374 lines
8.9 KiB
C
/*
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* linux/arch/arm/mach-sa1100/cpu-sa1110.c
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*
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* Copyright (C) 2001 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Note: there are two erratas that apply to the SA1110 here:
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* 7 - SDRAM auto-power-up failure (rev A0)
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* 13 - Corruption of internal register reads/writes following
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* SDRAM reads (rev A0, B0, B1)
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*
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* We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
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*
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* The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
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*/
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <asm/cputype.h>
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#include <asm/mach-types.h>
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#include <mach/generic.h>
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#include <mach/hardware.h>
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#undef DEBUG
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struct sdram_params {
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const char name[20];
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u_char rows; /* bits */
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u_char cas_latency; /* cycles */
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u_char tck; /* clock cycle time (ns) */
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u_char trcd; /* activate to r/w (ns) */
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u_char trp; /* precharge to activate (ns) */
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u_char twr; /* write recovery time (ns) */
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u_short refresh; /* refresh time for array (us) */
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};
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struct sdram_info {
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u_int mdcnfg;
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u_int mdrefr;
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u_int mdcas[3];
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};
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static struct sdram_params sdram_tbl[] __initdata = {
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{ /* Toshiba TC59SM716 CL2 */
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.name = "TC59SM716-CL2",
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.rows = 12,
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.tck = 10,
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.trcd = 20,
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.trp = 20,
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.twr = 10,
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.refresh = 64000,
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.cas_latency = 2,
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}, { /* Toshiba TC59SM716 CL3 */
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.name = "TC59SM716-CL3",
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.rows = 12,
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.tck = 8,
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.trcd = 20,
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.trp = 20,
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.twr = 8,
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.refresh = 64000,
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.cas_latency = 3,
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}, { /* Samsung K4S641632D TC75 */
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.name = "K4S641632D",
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.rows = 14,
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.tck = 9,
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.trcd = 27,
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.trp = 20,
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.twr = 9,
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.refresh = 64000,
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.cas_latency = 3,
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}, { /* Samsung K4S281632B-1H */
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.name = "K4S281632B-1H",
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.rows = 12,
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.tck = 10,
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.trp = 20,
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.twr = 10,
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.refresh = 64000,
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.cas_latency = 3,
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}, { /* Samsung KM416S4030CT */
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.name = "KM416S4030CT",
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.rows = 13,
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.tck = 8,
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.trcd = 24, /* 3 CLKs */
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.trp = 24, /* 3 CLKs */
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.twr = 16, /* Trdl: 2 CLKs */
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.refresh = 64000,
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.cas_latency = 3,
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}, { /* Winbond W982516AH75L CL3 */
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.name = "W982516AH75L",
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.rows = 16,
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.tck = 8,
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.trcd = 20,
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.trp = 20,
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.twr = 8,
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.refresh = 64000,
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.cas_latency = 3,
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}, { /* Micron MT48LC8M16A2TG-75 */
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.name = "MT48LC8M16A2TG-75",
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.rows = 12,
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.tck = 8,
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.trcd = 20,
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.trp = 20,
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.twr = 8,
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.refresh = 64000,
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.cas_latency = 3,
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},
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};
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static struct sdram_params sdram_params;
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/*
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* Given a period in ns and frequency in khz, calculate the number of
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* cycles of frequency in period. Note that we round up to the next
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* cycle, even if we are only slightly over.
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*/
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static inline u_int ns_to_cycles(u_int ns, u_int khz)
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{
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return (ns * khz + 999999) / 1000000;
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}
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/*
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* Create the MDCAS register bit pattern.
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*/
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static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
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{
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u_int shift;
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rcd = 2 * rcd - 1;
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shift = delayed + 1 + rcd;
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mdcas[0] = (1 << rcd) - 1;
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mdcas[0] |= 0x55555555 << shift;
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mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
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}
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static void
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sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
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struct sdram_params *sdram)
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{
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u_int mem_khz, sd_khz, trp, twr;
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mem_khz = cpu_khz / 2;
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sd_khz = mem_khz;
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/*
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* If SDCLK would invalidate the SDRAM timings,
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* run SDCLK at half speed.
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*
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* CPU steppings prior to B2 must either run the memory at
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* half speed or use delayed read latching (errata 13).
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*/
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if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
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(CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
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sd_khz /= 2;
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sd->mdcnfg = MDCNFG & 0x007f007f;
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twr = ns_to_cycles(sdram->twr, mem_khz);
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/* trp should always be >1 */
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trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
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if (trp < 1)
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trp = 1;
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sd->mdcnfg |= trp << 8;
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sd->mdcnfg |= trp << 24;
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sd->mdcnfg |= sdram->cas_latency << 12;
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sd->mdcnfg |= sdram->cas_latency << 28;
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sd->mdcnfg |= twr << 14;
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sd->mdcnfg |= twr << 30;
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sd->mdrefr = MDREFR & 0xffbffff0;
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sd->mdrefr |= 7;
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if (sd_khz != mem_khz)
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sd->mdrefr |= MDREFR_K1DB2;
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/* initial number of '1's in MDCAS + 1 */
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set_mdcas(sd->mdcas, sd_khz >= 62000,
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ns_to_cycles(sdram->trcd, mem_khz));
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#ifdef DEBUG
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printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
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sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
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sd->mdcas[2]);
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#endif
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}
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/*
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* Set the SDRAM refresh rate.
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*/
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static inline void sdram_set_refresh(u_int dri)
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{
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MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
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(void) MDREFR;
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}
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/*
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* Update the refresh period. We do this such that we always refresh
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* the SDRAMs within their permissible period. The refresh period is
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* always a multiple of the memory clock (fixed at cpu_clock / 2).
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*
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* FIXME: we don't currently take account of burst accesses here,
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* but neither do Intels DM nor Angel.
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*/
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static void
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sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
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{
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u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
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u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
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#ifdef DEBUG
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mdelay(250);
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printk(KERN_DEBUG "new dri value = %d\n", dri);
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#endif
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sdram_set_refresh(dri);
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}
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/*
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* Ok, set the CPU frequency.
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*/
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static int sa1110_target(struct cpufreq_policy *policy, unsigned int ppcr)
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{
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struct sdram_params *sdram = &sdram_params;
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struct sdram_info sd;
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unsigned long flags;
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unsigned int unused;
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sdram_calculate_timing(&sd, sa11x0_freq_table[ppcr].frequency, sdram);
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#if 0
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/*
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* These values are wrong according to the SA1110 documentation
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* and errata, but they seem to work. Need to get a storage
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* scope on to the SDRAM signals to work out why.
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*/
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if (policy->max < 147500) {
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sd.mdrefr |= MDREFR_K1DB2;
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sd.mdcas[0] = 0xaaaaaa7f;
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} else {
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sd.mdrefr &= ~MDREFR_K1DB2;
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sd.mdcas[0] = 0xaaaaaa9f;
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}
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sd.mdcas[1] = 0xaaaaaaaa;
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sd.mdcas[2] = 0xaaaaaaaa;
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#endif
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/*
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* The clock could be going away for some time. Set the SDRAMs
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* to refresh rapidly (every 64 memory clock cycles). To get
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* through the whole array, we need to wait 262144 mclk cycles.
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* We wait 20ms to be safe.
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*/
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sdram_set_refresh(2);
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if (!irqs_disabled())
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msleep(20);
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else
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mdelay(20);
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/*
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* Reprogram the DRAM timings with interrupts disabled, and
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* ensure that we are doing this within a complete cache line.
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* This means that we won't access SDRAM for the duration of
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* the programming.
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*/
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local_irq_save(flags);
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asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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udelay(10);
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__asm__ __volatile__("\n\
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b 2f \n\
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.align 5 \n\
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1: str %3, [%1, #0] @ MDCNFG \n\
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str %4, [%1, #28] @ MDREFR \n\
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str %5, [%1, #4] @ MDCAS0 \n\
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str %6, [%1, #8] @ MDCAS1 \n\
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str %7, [%1, #12] @ MDCAS2 \n\
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str %8, [%2, #0] @ PPCR \n\
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ldr %0, [%1, #0] \n\
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b 3f \n\
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2: b 1b \n\
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3: nop \n\
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nop"
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: "=&r" (unused)
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: "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
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"r" (sd.mdrefr), "r" (sd.mdcas[0]),
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"r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
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local_irq_restore(flags);
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/*
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* Now, return the SDRAM refresh back to normal.
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*/
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sdram_update_refresh(sa11x0_freq_table[ppcr].frequency, sdram);
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return 0;
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}
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static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
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{
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return cpufreq_generic_init(policy, sa11x0_freq_table, CPUFREQ_ETERNAL);
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}
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/* sa1110_driver needs __refdata because it must remain after init registers
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* it with cpufreq_register_driver() */
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static struct cpufreq_driver sa1110_driver __refdata = {
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.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = sa1110_target,
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.get = sa11x0_getspeed,
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.init = sa1110_cpu_init,
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.name = "sa1110",
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};
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static struct sdram_params *sa1110_find_sdram(const char *name)
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{
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struct sdram_params *sdram;
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for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
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sdram++)
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if (strcmp(name, sdram->name) == 0)
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return sdram;
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return NULL;
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}
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static char sdram_name[16];
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static int __init sa1110_clk_init(void)
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{
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struct sdram_params *sdram;
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const char *name = sdram_name;
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if (!cpu_is_sa1110())
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return -ENODEV;
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if (!name[0]) {
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if (machine_is_assabet())
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name = "TC59SM716-CL3";
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if (machine_is_pt_system3())
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name = "K4S641632D";
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if (machine_is_h3100())
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name = "KM416S4030CT";
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if (machine_is_jornada720())
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name = "K4S281632B-1H";
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if (machine_is_nanoengine())
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name = "MT48LC8M16A2TG-75";
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}
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sdram = sa1110_find_sdram(name);
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if (sdram) {
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printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
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" twr: %d refresh: %d cas_latency: %d\n",
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sdram->tck, sdram->trcd, sdram->trp,
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sdram->twr, sdram->refresh, sdram->cas_latency);
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memcpy(&sdram_params, sdram, sizeof(sdram_params));
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return cpufreq_register_driver(&sa1110_driver);
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}
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return 0;
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}
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module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
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arch_initcall(sa1110_clk_init);
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