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![Daniel Mack](/assets/img/avatar_default.png)
A channel can accommodate more than one transaction, each consisting of multiple descriptors, the last of which has the DCMD_ENDIRQEN bit set. In order to report the channel's residue, we hence have to walk the list of running descriptors, look for those which match the cookie, and then try to find the descriptor which defines upper and lower boundaries that embrace the current transport pointer. Once it is found, walk forward until we find the descriptor that tells us about the end of a transaction via a set DCMD_ENDIRQEN bit. Signed-off-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
1126 lines
28 KiB
C
1126 lines
28 KiB
C
/*
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* Copyright 2012 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/platform_data/mmp_dma.h>
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#include <linux/dmapool.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/of.h>
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#include <linux/dma/mmp-pdma.h>
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#include "dmaengine.h"
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#define DCSR 0x0000
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#define DALGN 0x00a0
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#define DINT 0x00f0
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#define DDADR 0x0200
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#define DSADR(n) (0x0204 + ((n) << 4))
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#define DTADR(n) (0x0208 + ((n) << 4))
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#define DCMD 0x020c
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#define DCSR_RUN BIT(31) /* Run Bit (read / write) */
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#define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
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#define DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (read / write) */
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#define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
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#define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
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#define DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */
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#define DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */
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#define DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */
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#define DCSR_EORIRQEN BIT(28) /* End of Receive Interrupt Enable (R/W) */
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#define DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */
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#define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
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#define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
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#define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
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#define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
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#define DCSR_EORINTR BIT(9) /* The end of Receive */
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#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2))
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#define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */
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#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
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#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
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#define DDADR_STOP BIT(0) /* Stop (read / write) */
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#define DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */
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#define DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */
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#define DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */
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#define DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */
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#define DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */
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#define DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */
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#define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
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#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
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#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
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#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
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#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
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#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
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#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
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#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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#define PDMA_ALIGNMENT 3
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#define PDMA_MAX_DESC_BYTES DCMD_LENGTH
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struct mmp_pdma_desc_hw {
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u32 ddadr; /* Points to the next descriptor + flags */
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u32 dsadr; /* DSADR value for the current transfer */
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u32 dtadr; /* DTADR value for the current transfer */
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u32 dcmd; /* DCMD value for the current transfer */
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} __aligned(32);
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struct mmp_pdma_desc_sw {
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struct mmp_pdma_desc_hw desc;
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struct list_head node;
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struct list_head tx_list;
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struct dma_async_tx_descriptor async_tx;
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};
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struct mmp_pdma_phy;
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struct mmp_pdma_chan {
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struct device *dev;
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struct dma_chan chan;
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struct dma_async_tx_descriptor desc;
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struct mmp_pdma_phy *phy;
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enum dma_transfer_direction dir;
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struct mmp_pdma_desc_sw *cyclic_first; /* first desc_sw if channel
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* is in cyclic mode */
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/* channel's basic info */
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struct tasklet_struct tasklet;
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u32 dcmd;
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u32 drcmr;
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u32 dev_addr;
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/* list for desc */
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spinlock_t desc_lock; /* Descriptor list lock */
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struct list_head chain_pending; /* Link descriptors queue for pending */
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struct list_head chain_running; /* Link descriptors queue for running */
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bool idle; /* channel statue machine */
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bool byte_align;
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struct dma_pool *desc_pool; /* Descriptors pool */
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};
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struct mmp_pdma_phy {
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int idx;
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void __iomem *base;
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struct mmp_pdma_chan *vchan;
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};
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struct mmp_pdma_device {
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int dma_channels;
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void __iomem *base;
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struct device *dev;
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struct dma_device device;
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struct mmp_pdma_phy *phy;
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spinlock_t phy_lock; /* protect alloc/free phy channels */
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};
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#define tx_to_mmp_pdma_desc(tx) \
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container_of(tx, struct mmp_pdma_desc_sw, async_tx)
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#define to_mmp_pdma_desc(lh) \
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container_of(lh, struct mmp_pdma_desc_sw, node)
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#define to_mmp_pdma_chan(dchan) \
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container_of(dchan, struct mmp_pdma_chan, chan)
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#define to_mmp_pdma_dev(dmadev) \
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container_of(dmadev, struct mmp_pdma_device, device)
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static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
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{
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u32 reg = (phy->idx << 4) + DDADR;
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writel(addr, phy->base + reg);
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}
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static void enable_chan(struct mmp_pdma_phy *phy)
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{
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u32 reg, dalgn;
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if (!phy->vchan)
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return;
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reg = DRCMR(phy->vchan->drcmr);
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writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
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dalgn = readl(phy->base + DALGN);
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if (phy->vchan->byte_align)
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dalgn |= 1 << phy->idx;
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else
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dalgn &= ~(1 << phy->idx);
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writel(dalgn, phy->base + DALGN);
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reg = (phy->idx << 2) + DCSR;
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writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg);
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}
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static void disable_chan(struct mmp_pdma_phy *phy)
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{
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u32 reg;
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if (!phy)
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return;
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reg = (phy->idx << 2) + DCSR;
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writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg);
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}
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static int clear_chan_irq(struct mmp_pdma_phy *phy)
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{
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u32 dcsr;
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u32 dint = readl(phy->base + DINT);
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u32 reg = (phy->idx << 2) + DCSR;
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if (!(dint & BIT(phy->idx)))
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return -EAGAIN;
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/* clear irq */
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dcsr = readl(phy->base + reg);
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writel(dcsr, phy->base + reg);
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if ((dcsr & DCSR_BUSERR) && (phy->vchan))
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dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
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return 0;
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}
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static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id)
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{
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struct mmp_pdma_phy *phy = dev_id;
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if (clear_chan_irq(phy) != 0)
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return IRQ_NONE;
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tasklet_schedule(&phy->vchan->tasklet);
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return IRQ_HANDLED;
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}
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static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)
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{
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struct mmp_pdma_device *pdev = dev_id;
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struct mmp_pdma_phy *phy;
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u32 dint = readl(pdev->base + DINT);
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int i, ret;
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int irq_num = 0;
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while (dint) {
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i = __ffs(dint);
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dint &= (dint - 1);
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phy = &pdev->phy[i];
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ret = mmp_pdma_chan_handler(irq, phy);
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if (ret == IRQ_HANDLED)
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irq_num++;
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}
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if (irq_num)
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return IRQ_HANDLED;
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return IRQ_NONE;
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}
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/* lookup free phy channel as descending priority */
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static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan)
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{
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int prio, i;
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struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
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struct mmp_pdma_phy *phy, *found = NULL;
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unsigned long flags;
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/*
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* dma channel priorities
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* ch 0 - 3, 16 - 19 <--> (0)
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* ch 4 - 7, 20 - 23 <--> (1)
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* ch 8 - 11, 24 - 27 <--> (2)
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* ch 12 - 15, 28 - 31 <--> (3)
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*/
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spin_lock_irqsave(&pdev->phy_lock, flags);
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for (prio = 0; prio <= ((pdev->dma_channels - 1) & 0xf) >> 2; prio++) {
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for (i = 0; i < pdev->dma_channels; i++) {
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if (prio != (i & 0xf) >> 2)
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continue;
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phy = &pdev->phy[i];
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if (!phy->vchan) {
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phy->vchan = pchan;
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found = phy;
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goto out_unlock;
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}
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}
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}
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out_unlock:
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spin_unlock_irqrestore(&pdev->phy_lock, flags);
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return found;
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}
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static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan)
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{
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struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
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unsigned long flags;
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u32 reg;
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if (!pchan->phy)
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return;
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/* clear the channel mapping in DRCMR */
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reg = DRCMR(pchan->drcmr);
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writel(0, pchan->phy->base + reg);
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spin_lock_irqsave(&pdev->phy_lock, flags);
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pchan->phy->vchan = NULL;
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pchan->phy = NULL;
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spin_unlock_irqrestore(&pdev->phy_lock, flags);
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}
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/**
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* start_pending_queue - transfer any pending transactions
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* pending list ==> running list
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*/
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static void start_pending_queue(struct mmp_pdma_chan *chan)
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{
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struct mmp_pdma_desc_sw *desc;
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/* still in running, irq will start the pending list */
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if (!chan->idle) {
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dev_dbg(chan->dev, "DMA controller still busy\n");
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return;
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}
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if (list_empty(&chan->chain_pending)) {
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/* chance to re-fetch phy channel with higher prio */
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mmp_pdma_free_phy(chan);
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dev_dbg(chan->dev, "no pending list\n");
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return;
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}
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if (!chan->phy) {
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chan->phy = lookup_phy(chan);
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if (!chan->phy) {
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dev_dbg(chan->dev, "no free dma channel\n");
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return;
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}
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}
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/*
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* pending -> running
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* reintilize pending list
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*/
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desc = list_first_entry(&chan->chain_pending,
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struct mmp_pdma_desc_sw, node);
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list_splice_tail_init(&chan->chain_pending, &chan->chain_running);
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/*
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* Program the descriptor's address into the DMA controller,
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* then start the DMA transaction
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*/
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set_desc(chan->phy, desc->async_tx.phys);
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enable_chan(chan->phy);
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chan->idle = false;
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}
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/* desc->tx_list ==> pending list */
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static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan);
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struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx);
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struct mmp_pdma_desc_sw *child;
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unsigned long flags;
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dma_cookie_t cookie = -EBUSY;
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spin_lock_irqsave(&chan->desc_lock, flags);
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list_for_each_entry(child, &desc->tx_list, node) {
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cookie = dma_cookie_assign(&child->async_tx);
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}
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/* softly link to pending list - desc->tx_list ==> pending list */
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list_splice_tail_init(&desc->tx_list, &chan->chain_pending);
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spin_unlock_irqrestore(&chan->desc_lock, flags);
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return cookie;
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}
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static struct mmp_pdma_desc_sw *
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mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan)
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{
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struct mmp_pdma_desc_sw *desc;
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dma_addr_t pdesc;
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desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
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if (!desc) {
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dev_err(chan->dev, "out of memory for link descriptor\n");
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return NULL;
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}
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memset(desc, 0, sizeof(*desc));
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INIT_LIST_HEAD(&desc->tx_list);
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dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
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/* each desc has submit */
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desc->async_tx.tx_submit = mmp_pdma_tx_submit;
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desc->async_tx.phys = pdesc;
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return desc;
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}
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/**
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* mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel.
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*
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* This function will create a dma pool for descriptor allocation.
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* Request irq only when channel is requested
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* Return - The number of allocated descriptors.
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*/
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static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
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{
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struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
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if (chan->desc_pool)
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return 1;
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chan->desc_pool = dma_pool_create(dev_name(&dchan->dev->device),
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chan->dev,
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sizeof(struct mmp_pdma_desc_sw),
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__alignof__(struct mmp_pdma_desc_sw),
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0);
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if (!chan->desc_pool) {
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dev_err(chan->dev, "unable to allocate descriptor pool\n");
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return -ENOMEM;
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}
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mmp_pdma_free_phy(chan);
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chan->idle = true;
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chan->dev_addr = 0;
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return 1;
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}
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static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan,
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struct list_head *list)
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{
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struct mmp_pdma_desc_sw *desc, *_desc;
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list_for_each_entry_safe(desc, _desc, list, node) {
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list_del(&desc->node);
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dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
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}
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}
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static void mmp_pdma_free_chan_resources(struct dma_chan *dchan)
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{
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struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
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unsigned long flags;
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spin_lock_irqsave(&chan->desc_lock, flags);
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mmp_pdma_free_desc_list(chan, &chan->chain_pending);
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mmp_pdma_free_desc_list(chan, &chan->chain_running);
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spin_unlock_irqrestore(&chan->desc_lock, flags);
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dma_pool_destroy(chan->desc_pool);
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chan->desc_pool = NULL;
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chan->idle = true;
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chan->dev_addr = 0;
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mmp_pdma_free_phy(chan);
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return;
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}
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static struct dma_async_tx_descriptor *
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mmp_pdma_prep_memcpy(struct dma_chan *dchan,
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dma_addr_t dma_dst, dma_addr_t dma_src,
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size_t len, unsigned long flags)
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{
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struct mmp_pdma_chan *chan;
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struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
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size_t copy = 0;
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if (!dchan)
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return NULL;
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if (!len)
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return NULL;
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chan = to_mmp_pdma_chan(dchan);
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chan->byte_align = false;
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if (!chan->dir) {
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chan->dir = DMA_MEM_TO_MEM;
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chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR;
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chan->dcmd |= DCMD_BURST32;
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}
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do {
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/* Allocate the link descriptor from DMA pool */
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new = mmp_pdma_alloc_descriptor(chan);
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if (!new) {
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dev_err(chan->dev, "no memory for desc\n");
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goto fail;
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}
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copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
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if (dma_src & 0x7 || dma_dst & 0x7)
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chan->byte_align = true;
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|
|
new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
|
|
new->desc.dsadr = dma_src;
|
|
new->desc.dtadr = dma_dst;
|
|
|
|
if (!first)
|
|
first = new;
|
|
else
|
|
prev->desc.ddadr = new->async_tx.phys;
|
|
|
|
new->async_tx.cookie = 0;
|
|
async_tx_ack(&new->async_tx);
|
|
|
|
prev = new;
|
|
len -= copy;
|
|
|
|
if (chan->dir == DMA_MEM_TO_DEV) {
|
|
dma_src += copy;
|
|
} else if (chan->dir == DMA_DEV_TO_MEM) {
|
|
dma_dst += copy;
|
|
} else if (chan->dir == DMA_MEM_TO_MEM) {
|
|
dma_src += copy;
|
|
dma_dst += copy;
|
|
}
|
|
|
|
/* Insert the link descriptor to the LD ring */
|
|
list_add_tail(&new->node, &first->tx_list);
|
|
} while (len);
|
|
|
|
first->async_tx.flags = flags; /* client is in control of this ack */
|
|
first->async_tx.cookie = -EBUSY;
|
|
|
|
/* last desc and fire IRQ */
|
|
new->desc.ddadr = DDADR_STOP;
|
|
new->desc.dcmd |= DCMD_ENDIRQEN;
|
|
|
|
chan->cyclic_first = NULL;
|
|
|
|
return &first->async_tx;
|
|
|
|
fail:
|
|
if (first)
|
|
mmp_pdma_free_desc_list(chan, &first->tx_list);
|
|
return NULL;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
|
|
unsigned int sg_len, enum dma_transfer_direction dir,
|
|
unsigned long flags, void *context)
|
|
{
|
|
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
|
|
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
|
|
size_t len, avail;
|
|
struct scatterlist *sg;
|
|
dma_addr_t addr;
|
|
int i;
|
|
|
|
if ((sgl == NULL) || (sg_len == 0))
|
|
return NULL;
|
|
|
|
chan->byte_align = false;
|
|
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
addr = sg_dma_address(sg);
|
|
avail = sg_dma_len(sgl);
|
|
|
|
do {
|
|
len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
|
|
if (addr & 0x7)
|
|
chan->byte_align = true;
|
|
|
|
/* allocate and populate the descriptor */
|
|
new = mmp_pdma_alloc_descriptor(chan);
|
|
if (!new) {
|
|
dev_err(chan->dev, "no memory for desc\n");
|
|
goto fail;
|
|
}
|
|
|
|
new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
|
|
if (dir == DMA_MEM_TO_DEV) {
|
|
new->desc.dsadr = addr;
|
|
new->desc.dtadr = chan->dev_addr;
|
|
} else {
|
|
new->desc.dsadr = chan->dev_addr;
|
|
new->desc.dtadr = addr;
|
|
}
|
|
|
|
if (!first)
|
|
first = new;
|
|
else
|
|
prev->desc.ddadr = new->async_tx.phys;
|
|
|
|
new->async_tx.cookie = 0;
|
|
async_tx_ack(&new->async_tx);
|
|
prev = new;
|
|
|
|
/* Insert the link descriptor to the LD ring */
|
|
list_add_tail(&new->node, &first->tx_list);
|
|
|
|
/* update metadata */
|
|
addr += len;
|
|
avail -= len;
|
|
} while (avail);
|
|
}
|
|
|
|
first->async_tx.cookie = -EBUSY;
|
|
first->async_tx.flags = flags;
|
|
|
|
/* last desc and fire IRQ */
|
|
new->desc.ddadr = DDADR_STOP;
|
|
new->desc.dcmd |= DCMD_ENDIRQEN;
|
|
|
|
chan->dir = dir;
|
|
chan->cyclic_first = NULL;
|
|
|
|
return &first->async_tx;
|
|
|
|
fail:
|
|
if (first)
|
|
mmp_pdma_free_desc_list(chan, &first->tx_list);
|
|
return NULL;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
|
|
dma_addr_t buf_addr, size_t len, size_t period_len,
|
|
enum dma_transfer_direction direction,
|
|
unsigned long flags, void *context)
|
|
{
|
|
struct mmp_pdma_chan *chan;
|
|
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
|
|
dma_addr_t dma_src, dma_dst;
|
|
|
|
if (!dchan || !len || !period_len)
|
|
return NULL;
|
|
|
|
/* the buffer length must be a multiple of period_len */
|
|
if (len % period_len != 0)
|
|
return NULL;
|
|
|
|
if (period_len > PDMA_MAX_DESC_BYTES)
|
|
return NULL;
|
|
|
|
chan = to_mmp_pdma_chan(dchan);
|
|
|
|
switch (direction) {
|
|
case DMA_MEM_TO_DEV:
|
|
dma_src = buf_addr;
|
|
dma_dst = chan->dev_addr;
|
|
break;
|
|
case DMA_DEV_TO_MEM:
|
|
dma_dst = buf_addr;
|
|
dma_src = chan->dev_addr;
|
|
break;
|
|
default:
|
|
dev_err(chan->dev, "Unsupported direction for cyclic DMA\n");
|
|
return NULL;
|
|
}
|
|
|
|
chan->dir = direction;
|
|
|
|
do {
|
|
/* Allocate the link descriptor from DMA pool */
|
|
new = mmp_pdma_alloc_descriptor(chan);
|
|
if (!new) {
|
|
dev_err(chan->dev, "no memory for desc\n");
|
|
goto fail;
|
|
}
|
|
|
|
new->desc.dcmd = (chan->dcmd | DCMD_ENDIRQEN |
|
|
(DCMD_LENGTH & period_len));
|
|
new->desc.dsadr = dma_src;
|
|
new->desc.dtadr = dma_dst;
|
|
|
|
if (!first)
|
|
first = new;
|
|
else
|
|
prev->desc.ddadr = new->async_tx.phys;
|
|
|
|
new->async_tx.cookie = 0;
|
|
async_tx_ack(&new->async_tx);
|
|
|
|
prev = new;
|
|
len -= period_len;
|
|
|
|
if (chan->dir == DMA_MEM_TO_DEV)
|
|
dma_src += period_len;
|
|
else
|
|
dma_dst += period_len;
|
|
|
|
/* Insert the link descriptor to the LD ring */
|
|
list_add_tail(&new->node, &first->tx_list);
|
|
} while (len);
|
|
|
|
first->async_tx.flags = flags; /* client is in control of this ack */
|
|
first->async_tx.cookie = -EBUSY;
|
|
|
|
/* make the cyclic link */
|
|
new->desc.ddadr = first->async_tx.phys;
|
|
chan->cyclic_first = first;
|
|
|
|
return &first->async_tx;
|
|
|
|
fail:
|
|
if (first)
|
|
mmp_pdma_free_desc_list(chan, &first->tx_list);
|
|
return NULL;
|
|
}
|
|
|
|
static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
|
|
unsigned long arg)
|
|
{
|
|
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
|
|
struct dma_slave_config *cfg = (void *)arg;
|
|
unsigned long flags;
|
|
u32 maxburst = 0, addr = 0;
|
|
enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
|
|
|
|
if (!dchan)
|
|
return -EINVAL;
|
|
|
|
switch (cmd) {
|
|
case DMA_TERMINATE_ALL:
|
|
disable_chan(chan->phy);
|
|
mmp_pdma_free_phy(chan);
|
|
spin_lock_irqsave(&chan->desc_lock, flags);
|
|
mmp_pdma_free_desc_list(chan, &chan->chain_pending);
|
|
mmp_pdma_free_desc_list(chan, &chan->chain_running);
|
|
spin_unlock_irqrestore(&chan->desc_lock, flags);
|
|
chan->idle = true;
|
|
break;
|
|
case DMA_SLAVE_CONFIG:
|
|
if (cfg->direction == DMA_DEV_TO_MEM) {
|
|
chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
|
|
maxburst = cfg->src_maxburst;
|
|
width = cfg->src_addr_width;
|
|
addr = cfg->src_addr;
|
|
} else if (cfg->direction == DMA_MEM_TO_DEV) {
|
|
chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
|
|
maxburst = cfg->dst_maxburst;
|
|
width = cfg->dst_addr_width;
|
|
addr = cfg->dst_addr;
|
|
}
|
|
|
|
if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
|
|
chan->dcmd |= DCMD_WIDTH1;
|
|
else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
|
|
chan->dcmd |= DCMD_WIDTH2;
|
|
else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
|
|
chan->dcmd |= DCMD_WIDTH4;
|
|
|
|
if (maxburst == 8)
|
|
chan->dcmd |= DCMD_BURST8;
|
|
else if (maxburst == 16)
|
|
chan->dcmd |= DCMD_BURST16;
|
|
else if (maxburst == 32)
|
|
chan->dcmd |= DCMD_BURST32;
|
|
|
|
chan->dir = cfg->direction;
|
|
chan->dev_addr = addr;
|
|
/* FIXME: drivers should be ported over to use the filter
|
|
* function. Once that's done, the following two lines can
|
|
* be removed.
|
|
*/
|
|
if (cfg->slave_id)
|
|
chan->drcmr = cfg->slave_id;
|
|
break;
|
|
default:
|
|
return -ENOSYS;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
|
|
dma_cookie_t cookie)
|
|
{
|
|
struct mmp_pdma_desc_sw *sw;
|
|
u32 curr, residue = 0;
|
|
bool passed = false;
|
|
bool cyclic = chan->cyclic_first != NULL;
|
|
|
|
/*
|
|
* If the channel does not have a phy pointer anymore, it has already
|
|
* been completed. Therefore, its residue is 0.
|
|
*/
|
|
if (!chan->phy)
|
|
return 0;
|
|
|
|
if (chan->dir == DMA_DEV_TO_MEM)
|
|
curr = readl(chan->phy->base + DTADR(chan->phy->idx));
|
|
else
|
|
curr = readl(chan->phy->base + DSADR(chan->phy->idx));
|
|
|
|
list_for_each_entry(sw, &chan->chain_running, node) {
|
|
u32 start, end, len;
|
|
|
|
if (chan->dir == DMA_DEV_TO_MEM)
|
|
start = sw->desc.dtadr;
|
|
else
|
|
start = sw->desc.dsadr;
|
|
|
|
len = sw->desc.dcmd & DCMD_LENGTH;
|
|
end = start + len;
|
|
|
|
/*
|
|
* 'passed' will be latched once we found the descriptor which
|
|
* lies inside the boundaries of the curr pointer. All
|
|
* descriptors that occur in the list _after_ we found that
|
|
* partially handled descriptor are still to be processed and
|
|
* are hence added to the residual bytes counter.
|
|
*/
|
|
|
|
if (passed) {
|
|
residue += len;
|
|
} else if (curr >= start && curr <= end) {
|
|
residue += end - curr;
|
|
passed = true;
|
|
}
|
|
|
|
/*
|
|
* Descriptors that have the ENDIRQEN bit set mark the end of a
|
|
* transaction chain, and the cookie assigned with it has been
|
|
* returned previously from mmp_pdma_tx_submit().
|
|
*
|
|
* In case we have multiple transactions in the running chain,
|
|
* and the cookie does not match the one the user asked us
|
|
* about, reset the state variables and start over.
|
|
*
|
|
* This logic does not apply to cyclic transactions, where all
|
|
* descriptors have the ENDIRQEN bit set, and for which we
|
|
* can't have multiple transactions on one channel anyway.
|
|
*/
|
|
if (cyclic || !(sw->desc.dcmd & DCMD_ENDIRQEN))
|
|
continue;
|
|
|
|
if (sw->async_tx.cookie == cookie) {
|
|
return residue;
|
|
} else {
|
|
residue = 0;
|
|
passed = false;
|
|
}
|
|
}
|
|
|
|
/* We should only get here in case of cyclic transactions */
|
|
return residue;
|
|
}
|
|
|
|
static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan,
|
|
dma_cookie_t cookie,
|
|
struct dma_tx_state *txstate)
|
|
{
|
|
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
|
|
enum dma_status ret;
|
|
|
|
ret = dma_cookie_status(dchan, cookie, txstate);
|
|
if (likely(ret != DMA_ERROR))
|
|
dma_set_residue(txstate, mmp_pdma_residue(chan, cookie));
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* mmp_pdma_issue_pending - Issue the DMA start command
|
|
* pending list ==> running list
|
|
*/
|
|
static void mmp_pdma_issue_pending(struct dma_chan *dchan)
|
|
{
|
|
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&chan->desc_lock, flags);
|
|
start_pending_queue(chan);
|
|
spin_unlock_irqrestore(&chan->desc_lock, flags);
|
|
}
|
|
|
|
/*
|
|
* dma_do_tasklet
|
|
* Do call back
|
|
* Start pending list
|
|
*/
|
|
static void dma_do_tasklet(unsigned long data)
|
|
{
|
|
struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data;
|
|
struct mmp_pdma_desc_sw *desc, *_desc;
|
|
LIST_HEAD(chain_cleanup);
|
|
unsigned long flags;
|
|
|
|
if (chan->cyclic_first) {
|
|
dma_async_tx_callback cb = NULL;
|
|
void *cb_data = NULL;
|
|
|
|
spin_lock_irqsave(&chan->desc_lock, flags);
|
|
desc = chan->cyclic_first;
|
|
cb = desc->async_tx.callback;
|
|
cb_data = desc->async_tx.callback_param;
|
|
spin_unlock_irqrestore(&chan->desc_lock, flags);
|
|
|
|
if (cb)
|
|
cb(cb_data);
|
|
|
|
return;
|
|
}
|
|
|
|
/* submit pending list; callback for each desc; free desc */
|
|
spin_lock_irqsave(&chan->desc_lock, flags);
|
|
|
|
list_for_each_entry_safe(desc, _desc, &chan->chain_running, node) {
|
|
/*
|
|
* move the descriptors to a temporary list so we can drop
|
|
* the lock during the entire cleanup operation
|
|
*/
|
|
list_move(&desc->node, &chain_cleanup);
|
|
|
|
/*
|
|
* Look for the first list entry which has the ENDIRQEN flag
|
|
* set. That is the descriptor we got an interrupt for, so
|
|
* complete that transaction and its cookie.
|
|
*/
|
|
if (desc->desc.dcmd & DCMD_ENDIRQEN) {
|
|
dma_cookie_t cookie = desc->async_tx.cookie;
|
|
dma_cookie_complete(&desc->async_tx);
|
|
dev_dbg(chan->dev, "completed_cookie=%d\n", cookie);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The hardware is idle and ready for more when the
|
|
* chain_running list is empty.
|
|
*/
|
|
chan->idle = list_empty(&chan->chain_running);
|
|
|
|
/* Start any pending transactions automatically */
|
|
start_pending_queue(chan);
|
|
spin_unlock_irqrestore(&chan->desc_lock, flags);
|
|
|
|
/* Run the callback for each descriptor, in order */
|
|
list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) {
|
|
struct dma_async_tx_descriptor *txd = &desc->async_tx;
|
|
|
|
/* Remove from the list of transactions */
|
|
list_del(&desc->node);
|
|
/* Run the link descriptor callback function */
|
|
if (txd->callback)
|
|
txd->callback(txd->callback_param);
|
|
|
|
dma_pool_free(chan->desc_pool, desc, txd->phys);
|
|
}
|
|
}
|
|
|
|
static int mmp_pdma_remove(struct platform_device *op)
|
|
{
|
|
struct mmp_pdma_device *pdev = platform_get_drvdata(op);
|
|
|
|
dma_async_device_unregister(&pdev->device);
|
|
return 0;
|
|
}
|
|
|
|
static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev, int idx, int irq)
|
|
{
|
|
struct mmp_pdma_phy *phy = &pdev->phy[idx];
|
|
struct mmp_pdma_chan *chan;
|
|
int ret;
|
|
|
|
chan = devm_kzalloc(pdev->dev, sizeof(*chan), GFP_KERNEL);
|
|
if (chan == NULL)
|
|
return -ENOMEM;
|
|
|
|
phy->idx = idx;
|
|
phy->base = pdev->base;
|
|
|
|
if (irq) {
|
|
ret = devm_request_irq(pdev->dev, irq, mmp_pdma_chan_handler,
|
|
IRQF_SHARED, "pdma", phy);
|
|
if (ret) {
|
|
dev_err(pdev->dev, "channel request irq fail!\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
spin_lock_init(&chan->desc_lock);
|
|
chan->dev = pdev->dev;
|
|
chan->chan.device = &pdev->device;
|
|
tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
|
|
INIT_LIST_HEAD(&chan->chain_pending);
|
|
INIT_LIST_HEAD(&chan->chain_running);
|
|
|
|
/* register virt channel to dma engine */
|
|
list_add_tail(&chan->chan.device_node, &pdev->device.channels);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id mmp_pdma_dt_ids[] = {
|
|
{ .compatible = "marvell,pdma-1.0", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
|
|
|
|
static struct dma_chan *mmp_pdma_dma_xlate(struct of_phandle_args *dma_spec,
|
|
struct of_dma *ofdma)
|
|
{
|
|
struct mmp_pdma_device *d = ofdma->of_dma_data;
|
|
struct dma_chan *chan;
|
|
|
|
chan = dma_get_any_slave_channel(&d->device);
|
|
if (!chan)
|
|
return NULL;
|
|
|
|
to_mmp_pdma_chan(chan)->drcmr = dma_spec->args[0];
|
|
|
|
return chan;
|
|
}
|
|
|
|
static int mmp_pdma_probe(struct platform_device *op)
|
|
{
|
|
struct mmp_pdma_device *pdev;
|
|
const struct of_device_id *of_id;
|
|
struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
|
|
struct resource *iores;
|
|
int i, ret, irq = 0;
|
|
int dma_channels = 0, irq_num = 0;
|
|
|
|
pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
|
|
if (!pdev)
|
|
return -ENOMEM;
|
|
|
|
pdev->dev = &op->dev;
|
|
|
|
spin_lock_init(&pdev->phy_lock);
|
|
|
|
iores = platform_get_resource(op, IORESOURCE_MEM, 0);
|
|
pdev->base = devm_ioremap_resource(pdev->dev, iores);
|
|
if (IS_ERR(pdev->base))
|
|
return PTR_ERR(pdev->base);
|
|
|
|
of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev);
|
|
if (of_id)
|
|
of_property_read_u32(pdev->dev->of_node, "#dma-channels",
|
|
&dma_channels);
|
|
else if (pdata && pdata->dma_channels)
|
|
dma_channels = pdata->dma_channels;
|
|
else
|
|
dma_channels = 32; /* default 32 channel */
|
|
pdev->dma_channels = dma_channels;
|
|
|
|
for (i = 0; i < dma_channels; i++) {
|
|
if (platform_get_irq(op, i) > 0)
|
|
irq_num++;
|
|
}
|
|
|
|
pdev->phy = devm_kcalloc(pdev->dev, dma_channels, sizeof(*pdev->phy),
|
|
GFP_KERNEL);
|
|
if (pdev->phy == NULL)
|
|
return -ENOMEM;
|
|
|
|
INIT_LIST_HEAD(&pdev->device.channels);
|
|
|
|
if (irq_num != dma_channels) {
|
|
/* all chan share one irq, demux inside */
|
|
irq = platform_get_irq(op, 0);
|
|
ret = devm_request_irq(pdev->dev, irq, mmp_pdma_int_handler,
|
|
IRQF_SHARED, "pdma", pdev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < dma_channels; i++) {
|
|
irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
|
|
ret = mmp_pdma_chan_init(pdev, i, irq);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
|
|
dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, pdev->device.cap_mask);
|
|
dma_cap_set(DMA_PRIVATE, pdev->device.cap_mask);
|
|
pdev->device.dev = &op->dev;
|
|
pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources;
|
|
pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources;
|
|
pdev->device.device_tx_status = mmp_pdma_tx_status;
|
|
pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy;
|
|
pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg;
|
|
pdev->device.device_prep_dma_cyclic = mmp_pdma_prep_dma_cyclic;
|
|
pdev->device.device_issue_pending = mmp_pdma_issue_pending;
|
|
pdev->device.device_control = mmp_pdma_control;
|
|
pdev->device.copy_align = PDMA_ALIGNMENT;
|
|
|
|
if (pdev->dev->coherent_dma_mask)
|
|
dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
|
|
else
|
|
dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
|
|
|
|
ret = dma_async_device_register(&pdev->device);
|
|
if (ret) {
|
|
dev_err(pdev->device.dev, "unable to register\n");
|
|
return ret;
|
|
}
|
|
|
|
if (op->dev.of_node) {
|
|
/* Device-tree DMA controller registration */
|
|
ret = of_dma_controller_register(op->dev.of_node,
|
|
mmp_pdma_dma_xlate, pdev);
|
|
if (ret < 0) {
|
|
dev_err(&op->dev, "of_dma_controller_register failed\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
platform_set_drvdata(op, pdev);
|
|
dev_info(pdev->device.dev, "initialized %d channels\n", dma_channels);
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id mmp_pdma_id_table[] = {
|
|
{ "mmp-pdma", },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver mmp_pdma_driver = {
|
|
.driver = {
|
|
.name = "mmp-pdma",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mmp_pdma_dt_ids,
|
|
},
|
|
.id_table = mmp_pdma_id_table,
|
|
.probe = mmp_pdma_probe,
|
|
.remove = mmp_pdma_remove,
|
|
};
|
|
|
|
bool mmp_pdma_filter_fn(struct dma_chan *chan, void *param)
|
|
{
|
|
struct mmp_pdma_chan *c = to_mmp_pdma_chan(chan);
|
|
|
|
if (chan->device->dev->driver != &mmp_pdma_driver.driver)
|
|
return false;
|
|
|
|
c->drcmr = *(unsigned int *)param;
|
|
|
|
return true;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mmp_pdma_filter_fn);
|
|
|
|
module_platform_driver(mmp_pdma_driver);
|
|
|
|
MODULE_DESCRIPTION("MARVELL MMP Peripheral DMA Driver");
|
|
MODULE_AUTHOR("Marvell International Ltd.");
|
|
MODULE_LICENSE("GPL v2");
|