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![Dan Carpenter](/assets/img/avatar_default.png)
The ">" here should be ">=" or we are one step beyond the end of the
sdma->channels[] array.
Fixes: 2e041c9462
('dmaengine: sirf: enable generic dt binding for dma channels')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
958 lines
25 KiB
C
958 lines
25 KiB
C
/*
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* DMA controller driver for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/of_dma.h>
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#include <linux/sirfsoc_dma.h>
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#include "dmaengine.h"
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#define SIRFSOC_DMA_DESCRIPTORS 16
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#define SIRFSOC_DMA_CHANNELS 16
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#define SIRFSOC_DMA_CH_ADDR 0x00
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#define SIRFSOC_DMA_CH_XLEN 0x04
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#define SIRFSOC_DMA_CH_YLEN 0x08
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#define SIRFSOC_DMA_CH_CTRL 0x0C
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#define SIRFSOC_DMA_WIDTH_0 0x100
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#define SIRFSOC_DMA_CH_VALID 0x140
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#define SIRFSOC_DMA_CH_INT 0x144
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#define SIRFSOC_DMA_INT_EN 0x148
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#define SIRFSOC_DMA_INT_EN_CLR 0x14C
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#define SIRFSOC_DMA_CH_LOOP_CTRL 0x150
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#define SIRFSOC_DMA_CH_LOOP_CTRL_CLR 0x15C
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#define SIRFSOC_DMA_MODE_CTRL_BIT 4
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#define SIRFSOC_DMA_DIR_CTRL_BIT 5
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/* xlen and dma_width register is in 4 bytes boundary */
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#define SIRFSOC_DMA_WORD_LEN 4
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struct sirfsoc_dma_desc {
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struct dma_async_tx_descriptor desc;
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struct list_head node;
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/* SiRFprimaII 2D-DMA parameters */
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int xlen; /* DMA xlen */
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int ylen; /* DMA ylen */
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int width; /* DMA width */
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int dir;
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bool cyclic; /* is loop DMA? */
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u32 addr; /* DMA buffer address */
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};
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struct sirfsoc_dma_chan {
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struct dma_chan chan;
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struct list_head free;
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struct list_head prepared;
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struct list_head queued;
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struct list_head active;
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struct list_head completed;
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unsigned long happened_cyclic;
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unsigned long completed_cyclic;
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/* Lock for this structure */
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spinlock_t lock;
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int mode;
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};
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struct sirfsoc_dma_regs {
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u32 ctrl[SIRFSOC_DMA_CHANNELS];
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u32 interrupt_en;
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};
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struct sirfsoc_dma {
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struct dma_device dma;
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struct tasklet_struct tasklet;
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struct sirfsoc_dma_chan channels[SIRFSOC_DMA_CHANNELS];
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void __iomem *base;
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int irq;
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struct clk *clk;
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bool is_marco;
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struct sirfsoc_dma_regs regs_save;
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};
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#define DRV_NAME "sirfsoc_dma"
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static int sirfsoc_dma_runtime_suspend(struct device *dev);
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/* Convert struct dma_chan to struct sirfsoc_dma_chan */
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static inline
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struct sirfsoc_dma_chan *dma_chan_to_sirfsoc_dma_chan(struct dma_chan *c)
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{
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return container_of(c, struct sirfsoc_dma_chan, chan);
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}
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/* Convert struct dma_chan to struct sirfsoc_dma */
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static inline struct sirfsoc_dma *dma_chan_to_sirfsoc_dma(struct dma_chan *c)
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{
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struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(c);
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return container_of(schan, struct sirfsoc_dma, channels[c->chan_id]);
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}
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/* Execute all queued DMA descriptors */
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static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan)
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{
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struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
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int cid = schan->chan.chan_id;
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struct sirfsoc_dma_desc *sdesc = NULL;
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/*
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* lock has been held by functions calling this, so we don't hold
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* lock again
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*/
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sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc,
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node);
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/* Move the first queued descriptor to active list */
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list_move_tail(&sdesc->node, &schan->active);
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/* Start the DMA transfer */
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writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 +
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cid * 4);
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writel_relaxed(cid | (schan->mode << SIRFSOC_DMA_MODE_CTRL_BIT) |
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(sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT),
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sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL);
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writel_relaxed(sdesc->xlen, sdma->base + cid * 0x10 +
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SIRFSOC_DMA_CH_XLEN);
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writel_relaxed(sdesc->ylen, sdma->base + cid * 0x10 +
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SIRFSOC_DMA_CH_YLEN);
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writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) |
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(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
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/*
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* writel has an implict memory write barrier to make sure data is
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* flushed into memory before starting DMA
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*/
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writel(sdesc->addr >> 2, sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR);
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if (sdesc->cyclic) {
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writel((1 << cid) | 1 << (cid + 16) |
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readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL),
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sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
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schan->happened_cyclic = schan->completed_cyclic = 0;
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}
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}
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/* Interrupt handler */
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static irqreturn_t sirfsoc_dma_irq(int irq, void *data)
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{
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struct sirfsoc_dma *sdma = data;
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struct sirfsoc_dma_chan *schan;
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struct sirfsoc_dma_desc *sdesc = NULL;
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u32 is;
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int ch;
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is = readl(sdma->base + SIRFSOC_DMA_CH_INT);
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while ((ch = fls(is) - 1) >= 0) {
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is &= ~(1 << ch);
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writel_relaxed(1 << ch, sdma->base + SIRFSOC_DMA_CH_INT);
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schan = &sdma->channels[ch];
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spin_lock(&schan->lock);
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sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
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node);
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if (!sdesc->cyclic) {
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/* Execute queued descriptors */
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list_splice_tail_init(&schan->active, &schan->completed);
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if (!list_empty(&schan->queued))
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sirfsoc_dma_execute(schan);
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} else
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schan->happened_cyclic++;
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spin_unlock(&schan->lock);
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}
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/* Schedule tasklet */
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tasklet_schedule(&sdma->tasklet);
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return IRQ_HANDLED;
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}
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/* process completed descriptors */
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static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma)
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{
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dma_cookie_t last_cookie = 0;
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struct sirfsoc_dma_chan *schan;
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struct sirfsoc_dma_desc *sdesc;
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struct dma_async_tx_descriptor *desc;
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unsigned long flags;
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unsigned long happened_cyclic;
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LIST_HEAD(list);
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int i;
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for (i = 0; i < sdma->dma.chancnt; i++) {
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schan = &sdma->channels[i];
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/* Get all completed descriptors */
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spin_lock_irqsave(&schan->lock, flags);
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if (!list_empty(&schan->completed)) {
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list_splice_tail_init(&schan->completed, &list);
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spin_unlock_irqrestore(&schan->lock, flags);
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/* Execute callbacks and run dependencies */
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list_for_each_entry(sdesc, &list, node) {
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desc = &sdesc->desc;
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if (desc->callback)
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desc->callback(desc->callback_param);
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last_cookie = desc->cookie;
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dma_run_dependencies(desc);
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}
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/* Free descriptors */
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spin_lock_irqsave(&schan->lock, flags);
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list_splice_tail_init(&list, &schan->free);
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schan->chan.completed_cookie = last_cookie;
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spin_unlock_irqrestore(&schan->lock, flags);
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} else {
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/* for cyclic channel, desc is always in active list */
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sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
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node);
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if (!sdesc || (sdesc && !sdesc->cyclic)) {
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/* without active cyclic DMA */
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spin_unlock_irqrestore(&schan->lock, flags);
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continue;
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}
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/* cyclic DMA */
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happened_cyclic = schan->happened_cyclic;
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spin_unlock_irqrestore(&schan->lock, flags);
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desc = &sdesc->desc;
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while (happened_cyclic != schan->completed_cyclic) {
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if (desc->callback)
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desc->callback(desc->callback_param);
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schan->completed_cyclic++;
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}
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}
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}
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}
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/* DMA Tasklet */
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static void sirfsoc_dma_tasklet(unsigned long data)
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{
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struct sirfsoc_dma *sdma = (void *)data;
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sirfsoc_dma_process_completed(sdma);
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}
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/* Submit descriptor to hardware */
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static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
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{
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struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(txd->chan);
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struct sirfsoc_dma_desc *sdesc;
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unsigned long flags;
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dma_cookie_t cookie;
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sdesc = container_of(txd, struct sirfsoc_dma_desc, desc);
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spin_lock_irqsave(&schan->lock, flags);
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/* Move descriptor to queue */
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list_move_tail(&sdesc->node, &schan->queued);
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cookie = dma_cookie_assign(txd);
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spin_unlock_irqrestore(&schan->lock, flags);
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return cookie;
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}
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static int sirfsoc_dma_slave_config(struct sirfsoc_dma_chan *schan,
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struct dma_slave_config *config)
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{
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unsigned long flags;
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if ((config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
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(config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES))
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return -EINVAL;
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spin_lock_irqsave(&schan->lock, flags);
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schan->mode = (config->src_maxburst == 4 ? 1 : 0);
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spin_unlock_irqrestore(&schan->lock, flags);
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return 0;
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}
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static int sirfsoc_dma_terminate_all(struct sirfsoc_dma_chan *schan)
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{
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struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
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int cid = schan->chan.chan_id;
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unsigned long flags;
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spin_lock_irqsave(&schan->lock, flags);
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if (!sdma->is_marco) {
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writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) &
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~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
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writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL)
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& ~((1 << cid) | 1 << (cid + 16)),
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sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
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} else {
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writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR);
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writel_relaxed((1 << cid) | 1 << (cid + 16),
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sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR);
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}
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writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);
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list_splice_tail_init(&schan->active, &schan->free);
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list_splice_tail_init(&schan->queued, &schan->free);
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spin_unlock_irqrestore(&schan->lock, flags);
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return 0;
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}
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static int sirfsoc_dma_pause_chan(struct sirfsoc_dma_chan *schan)
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{
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struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
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int cid = schan->chan.chan_id;
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unsigned long flags;
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spin_lock_irqsave(&schan->lock, flags);
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if (!sdma->is_marco)
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writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL)
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& ~((1 << cid) | 1 << (cid + 16)),
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sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
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else
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writel_relaxed((1 << cid) | 1 << (cid + 16),
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sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR);
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spin_unlock_irqrestore(&schan->lock, flags);
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return 0;
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}
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static int sirfsoc_dma_resume_chan(struct sirfsoc_dma_chan *schan)
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{
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struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
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int cid = schan->chan.chan_id;
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unsigned long flags;
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spin_lock_irqsave(&schan->lock, flags);
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if (!sdma->is_marco)
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writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL)
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| ((1 << cid) | 1 << (cid + 16)),
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sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
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else
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writel_relaxed((1 << cid) | 1 << (cid + 16),
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sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
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spin_unlock_irqrestore(&schan->lock, flags);
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return 0;
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}
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static int sirfsoc_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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{
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struct dma_slave_config *config;
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struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
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switch (cmd) {
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case DMA_PAUSE:
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return sirfsoc_dma_pause_chan(schan);
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case DMA_RESUME:
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return sirfsoc_dma_resume_chan(schan);
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case DMA_TERMINATE_ALL:
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return sirfsoc_dma_terminate_all(schan);
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case DMA_SLAVE_CONFIG:
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config = (struct dma_slave_config *)arg;
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return sirfsoc_dma_slave_config(schan, config);
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default:
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break;
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}
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return -ENOSYS;
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}
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/* Alloc channel resources */
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static int sirfsoc_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
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struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
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struct sirfsoc_dma_desc *sdesc;
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unsigned long flags;
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LIST_HEAD(descs);
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int i;
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pm_runtime_get_sync(sdma->dma.dev);
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/* Alloc descriptors for this channel */
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for (i = 0; i < SIRFSOC_DMA_DESCRIPTORS; i++) {
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sdesc = kzalloc(sizeof(*sdesc), GFP_KERNEL);
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if (!sdesc) {
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dev_notice(sdma->dma.dev, "Memory allocation error. "
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"Allocated only %u descriptors\n", i);
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break;
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}
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dma_async_tx_descriptor_init(&sdesc->desc, chan);
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sdesc->desc.flags = DMA_CTRL_ACK;
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sdesc->desc.tx_submit = sirfsoc_dma_tx_submit;
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list_add_tail(&sdesc->node, &descs);
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}
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/* Return error only if no descriptors were allocated */
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if (i == 0)
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return -ENOMEM;
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spin_lock_irqsave(&schan->lock, flags);
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list_splice_tail_init(&descs, &schan->free);
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spin_unlock_irqrestore(&schan->lock, flags);
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return i;
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}
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/* Free channel resources */
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static void sirfsoc_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
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struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
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struct sirfsoc_dma_desc *sdesc, *tmp;
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unsigned long flags;
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LIST_HEAD(descs);
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spin_lock_irqsave(&schan->lock, flags);
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/* Channel must be idle */
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BUG_ON(!list_empty(&schan->prepared));
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BUG_ON(!list_empty(&schan->queued));
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BUG_ON(!list_empty(&schan->active));
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BUG_ON(!list_empty(&schan->completed));
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/* Move data */
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list_splice_tail_init(&schan->free, &descs);
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spin_unlock_irqrestore(&schan->lock, flags);
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/* Free descriptors */
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list_for_each_entry_safe(sdesc, tmp, &descs, node)
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kfree(sdesc);
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pm_runtime_put(sdma->dma.dev);
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}
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/* Send pending descriptor to hardware */
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static void sirfsoc_dma_issue_pending(struct dma_chan *chan)
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{
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struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&schan->lock, flags);
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if (list_empty(&schan->active) && !list_empty(&schan->queued))
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sirfsoc_dma_execute(schan);
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|
|
spin_unlock_irqrestore(&schan->lock, flags);
|
|
}
|
|
|
|
/* Check request completion status */
|
|
static enum dma_status
|
|
sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
|
struct dma_tx_state *txstate)
|
|
{
|
|
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
|
|
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
|
unsigned long flags;
|
|
enum dma_status ret;
|
|
struct sirfsoc_dma_desc *sdesc;
|
|
int cid = schan->chan.chan_id;
|
|
unsigned long dma_pos;
|
|
unsigned long dma_request_bytes;
|
|
unsigned long residue;
|
|
|
|
spin_lock_irqsave(&schan->lock, flags);
|
|
|
|
sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
|
|
node);
|
|
dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) *
|
|
(sdesc->width * SIRFSOC_DMA_WORD_LEN);
|
|
|
|
ret = dma_cookie_status(chan, cookie, txstate);
|
|
dma_pos = readl_relaxed(sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR)
|
|
<< 2;
|
|
residue = dma_request_bytes - (dma_pos - sdesc->addr);
|
|
dma_set_residue(txstate, residue);
|
|
|
|
spin_unlock_irqrestore(&schan->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
|
|
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
|
unsigned long flags)
|
|
{
|
|
struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
|
|
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
|
struct sirfsoc_dma_desc *sdesc = NULL;
|
|
unsigned long iflags;
|
|
int ret;
|
|
|
|
if ((xt->dir != DMA_MEM_TO_DEV) && (xt->dir != DMA_DEV_TO_MEM)) {
|
|
ret = -EINVAL;
|
|
goto err_dir;
|
|
}
|
|
|
|
/* Get free descriptor */
|
|
spin_lock_irqsave(&schan->lock, iflags);
|
|
if (!list_empty(&schan->free)) {
|
|
sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
|
|
node);
|
|
list_del(&sdesc->node);
|
|
}
|
|
spin_unlock_irqrestore(&schan->lock, iflags);
|
|
|
|
if (!sdesc) {
|
|
/* try to free completed descriptors */
|
|
sirfsoc_dma_process_completed(sdma);
|
|
ret = 0;
|
|
goto no_desc;
|
|
}
|
|
|
|
/* Place descriptor in prepared list */
|
|
spin_lock_irqsave(&schan->lock, iflags);
|
|
|
|
/*
|
|
* Number of chunks in a frame can only be 1 for prima2
|
|
* and ylen (number of frame - 1) must be at least 0
|
|
*/
|
|
if ((xt->frame_size == 1) && (xt->numf > 0)) {
|
|
sdesc->cyclic = 0;
|
|
sdesc->xlen = xt->sgl[0].size / SIRFSOC_DMA_WORD_LEN;
|
|
sdesc->width = (xt->sgl[0].size + xt->sgl[0].icg) /
|
|
SIRFSOC_DMA_WORD_LEN;
|
|
sdesc->ylen = xt->numf - 1;
|
|
if (xt->dir == DMA_MEM_TO_DEV) {
|
|
sdesc->addr = xt->src_start;
|
|
sdesc->dir = 1;
|
|
} else {
|
|
sdesc->addr = xt->dst_start;
|
|
sdesc->dir = 0;
|
|
}
|
|
|
|
list_add_tail(&sdesc->node, &schan->prepared);
|
|
} else {
|
|
pr_err("sirfsoc DMA Invalid xfer\n");
|
|
ret = -EINVAL;
|
|
goto err_xfer;
|
|
}
|
|
spin_unlock_irqrestore(&schan->lock, iflags);
|
|
|
|
return &sdesc->desc;
|
|
err_xfer:
|
|
spin_unlock_irqrestore(&schan->lock, iflags);
|
|
no_desc:
|
|
err_dir:
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
sirfsoc_dma_prep_cyclic(struct dma_chan *chan, dma_addr_t addr,
|
|
size_t buf_len, size_t period_len,
|
|
enum dma_transfer_direction direction, unsigned long flags, void *context)
|
|
{
|
|
struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
|
|
struct sirfsoc_dma_desc *sdesc = NULL;
|
|
unsigned long iflags;
|
|
|
|
/*
|
|
* we only support cycle transfer with 2 period
|
|
* If the X-length is set to 0, it would be the loop mode.
|
|
* The DMA address keeps increasing until reaching the end of a loop
|
|
* area whose size is defined by (DMA_WIDTH x (Y_LENGTH + 1)). Then
|
|
* the DMA address goes back to the beginning of this area.
|
|
* In loop mode, the DMA data region is divided into two parts, BUFA
|
|
* and BUFB. DMA controller generates interrupts twice in each loop:
|
|
* when the DMA address reaches the end of BUFA or the end of the
|
|
* BUFB
|
|
*/
|
|
if (buf_len != 2 * period_len)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
/* Get free descriptor */
|
|
spin_lock_irqsave(&schan->lock, iflags);
|
|
if (!list_empty(&schan->free)) {
|
|
sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
|
|
node);
|
|
list_del(&sdesc->node);
|
|
}
|
|
spin_unlock_irqrestore(&schan->lock, iflags);
|
|
|
|
if (!sdesc)
|
|
return NULL;
|
|
|
|
/* Place descriptor in prepared list */
|
|
spin_lock_irqsave(&schan->lock, iflags);
|
|
sdesc->addr = addr;
|
|
sdesc->cyclic = 1;
|
|
sdesc->xlen = 0;
|
|
sdesc->ylen = buf_len / SIRFSOC_DMA_WORD_LEN - 1;
|
|
sdesc->width = 1;
|
|
list_add_tail(&sdesc->node, &schan->prepared);
|
|
spin_unlock_irqrestore(&schan->lock, iflags);
|
|
|
|
return &sdesc->desc;
|
|
}
|
|
|
|
/*
|
|
* The DMA controller consists of 16 independent DMA channels.
|
|
* Each channel is allocated to a different function
|
|
*/
|
|
bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id)
|
|
{
|
|
unsigned int ch_nr = (unsigned int) chan_id;
|
|
|
|
if (ch_nr == chan->chan_id +
|
|
chan->device->dev_id * SIRFSOC_DMA_CHANNELS)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(sirfsoc_dma_filter_id);
|
|
|
|
#define SIRFSOC_DMA_BUSWIDTHS \
|
|
(BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
|
|
|
|
static int sirfsoc_dma_device_slave_caps(struct dma_chan *dchan,
|
|
struct dma_slave_caps *caps)
|
|
{
|
|
caps->src_addr_widths = SIRFSOC_DMA_BUSWIDTHS;
|
|
caps->dstn_addr_widths = SIRFSOC_DMA_BUSWIDTHS;
|
|
caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
|
caps->cmd_pause = true;
|
|
caps->cmd_terminate = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct dma_chan *of_dma_sirfsoc_xlate(struct of_phandle_args *dma_spec,
|
|
struct of_dma *ofdma)
|
|
{
|
|
struct sirfsoc_dma *sdma = ofdma->of_dma_data;
|
|
unsigned int request = dma_spec->args[0];
|
|
|
|
if (request >= SIRFSOC_DMA_CHANNELS)
|
|
return NULL;
|
|
|
|
return dma_get_slave_channel(&sdma->channels[request].chan);
|
|
}
|
|
|
|
static int sirfsoc_dma_probe(struct platform_device *op)
|
|
{
|
|
struct device_node *dn = op->dev.of_node;
|
|
struct device *dev = &op->dev;
|
|
struct dma_device *dma;
|
|
struct sirfsoc_dma *sdma;
|
|
struct sirfsoc_dma_chan *schan;
|
|
struct resource res;
|
|
ulong regs_start, regs_size;
|
|
u32 id;
|
|
int ret, i;
|
|
|
|
sdma = devm_kzalloc(dev, sizeof(*sdma), GFP_KERNEL);
|
|
if (!sdma) {
|
|
dev_err(dev, "Memory exhausted!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (of_device_is_compatible(dn, "sirf,marco-dmac"))
|
|
sdma->is_marco = true;
|
|
|
|
if (of_property_read_u32(dn, "cell-index", &id)) {
|
|
dev_err(dev, "Fail to get DMAC index\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
sdma->irq = irq_of_parse_and_map(dn, 0);
|
|
if (sdma->irq == NO_IRQ) {
|
|
dev_err(dev, "Error mapping IRQ!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
sdma->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(sdma->clk)) {
|
|
dev_err(dev, "failed to get a clock.\n");
|
|
return PTR_ERR(sdma->clk);
|
|
}
|
|
|
|
ret = of_address_to_resource(dn, 0, &res);
|
|
if (ret) {
|
|
dev_err(dev, "Error parsing memory region!\n");
|
|
goto irq_dispose;
|
|
}
|
|
|
|
regs_start = res.start;
|
|
regs_size = resource_size(&res);
|
|
|
|
sdma->base = devm_ioremap(dev, regs_start, regs_size);
|
|
if (!sdma->base) {
|
|
dev_err(dev, "Error mapping memory region!\n");
|
|
ret = -ENOMEM;
|
|
goto irq_dispose;
|
|
}
|
|
|
|
ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma);
|
|
if (ret) {
|
|
dev_err(dev, "Error requesting IRQ!\n");
|
|
ret = -EINVAL;
|
|
goto irq_dispose;
|
|
}
|
|
|
|
dma = &sdma->dma;
|
|
dma->dev = dev;
|
|
dma->chancnt = SIRFSOC_DMA_CHANNELS;
|
|
|
|
dma->device_alloc_chan_resources = sirfsoc_dma_alloc_chan_resources;
|
|
dma->device_free_chan_resources = sirfsoc_dma_free_chan_resources;
|
|
dma->device_issue_pending = sirfsoc_dma_issue_pending;
|
|
dma->device_control = sirfsoc_dma_control;
|
|
dma->device_tx_status = sirfsoc_dma_tx_status;
|
|
dma->device_prep_interleaved_dma = sirfsoc_dma_prep_interleaved;
|
|
dma->device_prep_dma_cyclic = sirfsoc_dma_prep_cyclic;
|
|
dma->device_slave_caps = sirfsoc_dma_device_slave_caps;
|
|
|
|
INIT_LIST_HEAD(&dma->channels);
|
|
dma_cap_set(DMA_SLAVE, dma->cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, dma->cap_mask);
|
|
dma_cap_set(DMA_INTERLEAVE, dma->cap_mask);
|
|
dma_cap_set(DMA_PRIVATE, dma->cap_mask);
|
|
|
|
for (i = 0; i < dma->chancnt; i++) {
|
|
schan = &sdma->channels[i];
|
|
|
|
schan->chan.device = dma;
|
|
dma_cookie_init(&schan->chan);
|
|
|
|
INIT_LIST_HEAD(&schan->free);
|
|
INIT_LIST_HEAD(&schan->prepared);
|
|
INIT_LIST_HEAD(&schan->queued);
|
|
INIT_LIST_HEAD(&schan->active);
|
|
INIT_LIST_HEAD(&schan->completed);
|
|
|
|
spin_lock_init(&schan->lock);
|
|
list_add_tail(&schan->chan.device_node, &dma->channels);
|
|
}
|
|
|
|
tasklet_init(&sdma->tasklet, sirfsoc_dma_tasklet, (unsigned long)sdma);
|
|
|
|
/* Register DMA engine */
|
|
dev_set_drvdata(dev, sdma);
|
|
|
|
ret = dma_async_device_register(dma);
|
|
if (ret)
|
|
goto free_irq;
|
|
|
|
/* Device-tree DMA controller registration */
|
|
ret = of_dma_controller_register(dn, of_dma_sirfsoc_xlate, sdma);
|
|
if (ret) {
|
|
dev_err(dev, "failed to register DMA controller\n");
|
|
goto unreg_dma_dev;
|
|
}
|
|
|
|
pm_runtime_enable(&op->dev);
|
|
dev_info(dev, "initialized SIRFSOC DMAC driver\n");
|
|
|
|
return 0;
|
|
|
|
unreg_dma_dev:
|
|
dma_async_device_unregister(dma);
|
|
free_irq:
|
|
free_irq(sdma->irq, sdma);
|
|
irq_dispose:
|
|
irq_dispose_mapping(sdma->irq);
|
|
return ret;
|
|
}
|
|
|
|
static int sirfsoc_dma_remove(struct platform_device *op)
|
|
{
|
|
struct device *dev = &op->dev;
|
|
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
|
|
|
of_dma_controller_free(op->dev.of_node);
|
|
dma_async_device_unregister(&sdma->dma);
|
|
free_irq(sdma->irq, sdma);
|
|
irq_dispose_mapping(sdma->irq);
|
|
pm_runtime_disable(&op->dev);
|
|
if (!pm_runtime_status_suspended(&op->dev))
|
|
sirfsoc_dma_runtime_suspend(&op->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sirfsoc_dma_runtime_suspend(struct device *dev)
|
|
{
|
|
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(sdma->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int sirfsoc_dma_runtime_resume(struct device *dev)
|
|
{
|
|
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(sdma->clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "clk_enable failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int sirfsoc_dma_pm_suspend(struct device *dev)
|
|
{
|
|
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
|
struct sirfsoc_dma_regs *save = &sdma->regs_save;
|
|
struct sirfsoc_dma_desc *sdesc;
|
|
struct sirfsoc_dma_chan *schan;
|
|
int ch;
|
|
int ret;
|
|
|
|
/*
|
|
* if we were runtime-suspended before, resume to enable clock
|
|
* before accessing register
|
|
*/
|
|
if (pm_runtime_status_suspended(dev)) {
|
|
ret = sirfsoc_dma_runtime_resume(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* DMA controller will lose all registers while suspending
|
|
* so we need to save registers for active channels
|
|
*/
|
|
for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) {
|
|
schan = &sdma->channels[ch];
|
|
if (list_empty(&schan->active))
|
|
continue;
|
|
sdesc = list_first_entry(&schan->active,
|
|
struct sirfsoc_dma_desc,
|
|
node);
|
|
save->ctrl[ch] = readl_relaxed(sdma->base +
|
|
ch * 0x10 + SIRFSOC_DMA_CH_CTRL);
|
|
}
|
|
save->interrupt_en = readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN);
|
|
|
|
/* Disable clock */
|
|
sirfsoc_dma_runtime_suspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sirfsoc_dma_pm_resume(struct device *dev)
|
|
{
|
|
struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
|
|
struct sirfsoc_dma_regs *save = &sdma->regs_save;
|
|
struct sirfsoc_dma_desc *sdesc;
|
|
struct sirfsoc_dma_chan *schan;
|
|
int ch;
|
|
int ret;
|
|
|
|
/* Enable clock before accessing register */
|
|
ret = sirfsoc_dma_runtime_resume(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
writel_relaxed(save->interrupt_en, sdma->base + SIRFSOC_DMA_INT_EN);
|
|
for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) {
|
|
schan = &sdma->channels[ch];
|
|
if (list_empty(&schan->active))
|
|
continue;
|
|
sdesc = list_first_entry(&schan->active,
|
|
struct sirfsoc_dma_desc,
|
|
node);
|
|
writel_relaxed(sdesc->width,
|
|
sdma->base + SIRFSOC_DMA_WIDTH_0 + ch * 4);
|
|
writel_relaxed(sdesc->xlen,
|
|
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN);
|
|
writel_relaxed(sdesc->ylen,
|
|
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN);
|
|
writel_relaxed(save->ctrl[ch],
|
|
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL);
|
|
writel_relaxed(sdesc->addr >> 2,
|
|
sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR);
|
|
}
|
|
|
|
/* if we were runtime-suspended before, suspend again */
|
|
if (pm_runtime_status_suspended(dev))
|
|
sirfsoc_dma_runtime_suspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops sirfsoc_dma_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(sirfsoc_dma_runtime_suspend, sirfsoc_dma_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_dma_pm_suspend, sirfsoc_dma_pm_resume)
|
|
};
|
|
|
|
static struct of_device_id sirfsoc_dma_match[] = {
|
|
{ .compatible = "sirf,prima2-dmac", },
|
|
{ .compatible = "sirf,marco-dmac", },
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver sirfsoc_dma_driver = {
|
|
.probe = sirfsoc_dma_probe,
|
|
.remove = sirfsoc_dma_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.pm = &sirfsoc_dma_pm_ops,
|
|
.of_match_table = sirfsoc_dma_match,
|
|
},
|
|
};
|
|
|
|
static __init int sirfsoc_dma_init(void)
|
|
{
|
|
return platform_driver_register(&sirfsoc_dma_driver);
|
|
}
|
|
|
|
static void __exit sirfsoc_dma_exit(void)
|
|
{
|
|
platform_driver_unregister(&sirfsoc_dma_driver);
|
|
}
|
|
|
|
subsys_initcall(sirfsoc_dma_init);
|
|
module_exit(sirfsoc_dma_exit);
|
|
|
|
MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
|
|
"Barry Song <baohua.song@csr.com>");
|
|
MODULE_DESCRIPTION("SIRFSOC DMA control driver");
|
|
MODULE_LICENSE("GPL v2");
|