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![Jingoo Han](/assets/img/avatar_default.png)
The driver core clears the driver data to NULL after device_release or on probe failure. Thus, it is not needed to manually clear the device driver data to NULL. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
357 lines
8.9 KiB
C
357 lines
8.9 KiB
C
/*
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* Mailbox reservation modules for OMAP2/3
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*
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* Copyright (C) 2006-2009 Nokia Corporation
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* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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* and Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_data/mailbox-omap.h>
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#include "omap-mbox.h"
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#define MAILBOX_REVISION 0x000
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#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
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#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
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#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
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#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
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#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
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#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
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#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
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#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
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#define MBOX_REG_SIZE 0x120
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#define OMAP4_MBOX_REG_SIZE 0x130
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#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
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#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
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static void __iomem *mbox_base;
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struct omap_mbox2_fifo {
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unsigned long msg;
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unsigned long fifo_stat;
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unsigned long msg_stat;
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};
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struct omap_mbox2_priv {
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struct omap_mbox2_fifo tx_fifo;
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struct omap_mbox2_fifo rx_fifo;
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unsigned long irqenable;
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unsigned long irqstatus;
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u32 newmsg_bit;
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u32 notfull_bit;
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u32 ctx[OMAP4_MBOX_NR_REGS];
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unsigned long irqdisable;
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u32 intr_type;
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};
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static inline unsigned int mbox_read_reg(size_t ofs)
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{
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return __raw_readl(mbox_base + ofs);
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}
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static inline void mbox_write_reg(u32 val, size_t ofs)
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{
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__raw_writel(val, mbox_base + ofs);
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}
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/* Mailbox H/W preparations */
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static int omap2_mbox_startup(struct omap_mbox *mbox)
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{
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u32 l;
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pm_runtime_enable(mbox->dev->parent);
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pm_runtime_get_sync(mbox->dev->parent);
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l = mbox_read_reg(MAILBOX_REVISION);
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pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
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return 0;
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}
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static void omap2_mbox_shutdown(struct omap_mbox *mbox)
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{
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pm_runtime_put_sync(mbox->dev->parent);
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pm_runtime_disable(mbox->dev->parent);
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}
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/* Mailbox FIFO handle functions */
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static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_msg_t) mbox_read_reg(fifo->msg);
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}
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static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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mbox_write_reg(msg, fifo->msg);
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}
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static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_read_reg(fifo->msg_stat) == 0);
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}
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static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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return mbox_read_reg(fifo->fifo_stat);
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}
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/* Mailbox IRQ handle functions */
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static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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l = mbox_read_reg(p->irqenable);
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l |= bit;
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mbox_write_reg(l, p->irqenable);
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}
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static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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/*
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* Read and update the interrupt configuration register for pre-OMAP4.
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* OMAP4 and later SoCs have a dedicated interrupt disabling register.
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*/
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if (!p->intr_type)
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bit = mbox_read_reg(p->irqdisable) & ~bit;
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mbox_write_reg(bit, p->irqdisable);
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}
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static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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mbox_write_reg(bit, p->irqstatus);
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/* Flush posted write for irq status to avoid spurious interrupts */
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mbox_read_reg(p->irqstatus);
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}
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static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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u32 enable = mbox_read_reg(p->irqenable);
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u32 status = mbox_read_reg(p->irqstatus);
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return (int)(enable & status & bit);
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}
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static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
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{
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int i;
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struct omap_mbox2_priv *p = mbox->priv;
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int nr_regs;
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if (p->intr_type)
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nr_regs = OMAP4_MBOX_NR_REGS;
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else
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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p->ctx[i] = mbox_read_reg(i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
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i, p->ctx[i]);
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}
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}
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static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
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{
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int i;
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struct omap_mbox2_priv *p = mbox->priv;
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int nr_regs;
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if (p->intr_type)
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nr_regs = OMAP4_MBOX_NR_REGS;
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else
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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mbox_write_reg(p->ctx[i], i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
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i, p->ctx[i]);
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}
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}
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static struct omap_mbox_ops omap2_mbox_ops = {
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.type = OMAP_MBOX_TYPE2,
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.startup = omap2_mbox_startup,
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.shutdown = omap2_mbox_shutdown,
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.fifo_read = omap2_mbox_fifo_read,
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.fifo_write = omap2_mbox_fifo_write,
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.fifo_empty = omap2_mbox_fifo_empty,
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.fifo_full = omap2_mbox_fifo_full,
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.enable_irq = omap2_mbox_enable_irq,
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.disable_irq = omap2_mbox_disable_irq,
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.ack_irq = omap2_mbox_ack_irq,
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.is_irq = omap2_mbox_is_irq,
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.save_ctx = omap2_mbox_save_ctx,
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.restore_ctx = omap2_mbox_restore_ctx,
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};
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static int omap2_mbox_probe(struct platform_device *pdev)
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{
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struct resource *mem;
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int ret;
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struct omap_mbox **list, *mbox, *mboxblk;
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struct omap_mbox2_priv *priv, *privblk;
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struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
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struct omap_mbox_dev_info *info;
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int i;
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if (!pdata || !pdata->info_cnt || !pdata->info) {
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pr_err("%s: platform not supported\n", __func__);
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return -ENODEV;
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}
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/* allocate one extra for marking end of list */
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list = kzalloc((pdata->info_cnt + 1) * sizeof(*list), GFP_KERNEL);
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if (!list)
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return -ENOMEM;
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mboxblk = mbox = kzalloc(pdata->info_cnt * sizeof(*mbox), GFP_KERNEL);
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if (!mboxblk) {
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ret = -ENOMEM;
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goto free_list;
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}
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privblk = priv = kzalloc(pdata->info_cnt * sizeof(*priv), GFP_KERNEL);
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if (!privblk) {
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ret = -ENOMEM;
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goto free_mboxblk;
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}
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info = pdata->info;
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for (i = 0; i < pdata->info_cnt; i++, info++, priv++) {
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priv->tx_fifo.msg = MAILBOX_MESSAGE(info->tx_id);
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priv->tx_fifo.fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id);
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priv->rx_fifo.msg = MAILBOX_MESSAGE(info->rx_id);
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priv->rx_fifo.msg_stat = MAILBOX_MSGSTATUS(info->rx_id);
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priv->notfull_bit = MAILBOX_IRQ_NOTFULL(info->tx_id);
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priv->newmsg_bit = MAILBOX_IRQ_NEWMSG(info->rx_id);
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if (pdata->intr_type) {
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priv->irqenable = OMAP4_MAILBOX_IRQENABLE(info->usr_id);
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priv->irqstatus = OMAP4_MAILBOX_IRQSTATUS(info->usr_id);
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priv->irqdisable =
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OMAP4_MAILBOX_IRQENABLE_CLR(info->usr_id);
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} else {
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priv->irqenable = MAILBOX_IRQENABLE(info->usr_id);
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priv->irqstatus = MAILBOX_IRQSTATUS(info->usr_id);
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priv->irqdisable = MAILBOX_IRQENABLE(info->usr_id);
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}
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priv->intr_type = pdata->intr_type;
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mbox->priv = priv;
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mbox->name = info->name;
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mbox->ops = &omap2_mbox_ops;
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mbox->irq = platform_get_irq(pdev, info->irq_id);
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if (mbox->irq < 0) {
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ret = mbox->irq;
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goto free_privblk;
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}
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list[i] = mbox++;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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ret = -ENOENT;
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goto free_privblk;
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}
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mbox_base = ioremap(mem->start, resource_size(mem));
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if (!mbox_base) {
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ret = -ENOMEM;
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goto free_privblk;
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}
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ret = omap_mbox_register(&pdev->dev, list);
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if (ret)
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goto unmap_mbox;
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platform_set_drvdata(pdev, list);
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return 0;
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unmap_mbox:
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iounmap(mbox_base);
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free_privblk:
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kfree(privblk);
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free_mboxblk:
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kfree(mboxblk);
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free_list:
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kfree(list);
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return ret;
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}
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static int omap2_mbox_remove(struct platform_device *pdev)
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{
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struct omap_mbox2_priv *privblk;
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struct omap_mbox **list = platform_get_drvdata(pdev);
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struct omap_mbox *mboxblk = list[0];
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privblk = mboxblk->priv;
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omap_mbox_unregister();
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iounmap(mbox_base);
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kfree(privblk);
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kfree(mboxblk);
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kfree(list);
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return 0;
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}
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static struct platform_driver omap2_mbox_driver = {
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.probe = omap2_mbox_probe,
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.remove = omap2_mbox_remove,
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.driver = {
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.name = "omap-mailbox",
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},
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};
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static int __init omap2_mbox_init(void)
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{
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return platform_driver_register(&omap2_mbox_driver);
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}
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static void __exit omap2_mbox_exit(void)
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{
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platform_driver_unregister(&omap2_mbox_driver);
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}
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module_init(omap2_mbox_init);
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module_exit(omap2_mbox_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
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MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
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MODULE_AUTHOR("Paul Mundt");
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MODULE_ALIAS("platform:omap2-mailbox");
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