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![Jingoo Han](/assets/img/avatar_default.png)
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Reviewed-by: Michal Simek <monstr@monstr.eu> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
249 lines
6.4 KiB
C
249 lines
6.4 KiB
C
/*
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* Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
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*
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* (C) Copyright 2013 - 2014 Xilinx, Inc.
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* (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/watchdog.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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/* Register offsets for the Wdt device */
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#define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
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#define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
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#define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
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/* Control/Status Register Masks */
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#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */
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#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */
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#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
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/* Control/Status Register 0/1 bits */
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#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
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/* SelfTest constants */
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#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
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#define XWT_TIMER_FAILED 0xFFFFFFFF
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#define WATCHDOG_NAME "Xilinx Watchdog"
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struct xwdt_device {
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void __iomem *base;
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u32 wdt_interval;
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spinlock_t spinlock;
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struct watchdog_device xilinx_wdt_wdd;
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};
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static int xilinx_wdt_start(struct watchdog_device *wdd)
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{
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u32 control_status_reg;
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struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
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spin_lock(&xdev->spinlock);
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/* Clean previous status and enable the watchdog timer */
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control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
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control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
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iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
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xdev->base + XWT_TWCSR0_OFFSET);
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iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
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spin_unlock(&xdev->spinlock);
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return 0;
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}
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static int xilinx_wdt_stop(struct watchdog_device *wdd)
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{
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u32 control_status_reg;
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struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
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spin_lock(&xdev->spinlock);
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control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
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iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
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xdev->base + XWT_TWCSR0_OFFSET);
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iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
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spin_unlock(&xdev->spinlock);
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pr_info("Stopped!\n");
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return 0;
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}
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static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
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{
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u32 control_status_reg;
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struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
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spin_lock(&xdev->spinlock);
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control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
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control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
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iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
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spin_unlock(&xdev->spinlock);
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return 0;
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}
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static const struct watchdog_info xilinx_wdt_ident = {
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.options = WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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.firmware_version = 1,
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.identity = WATCHDOG_NAME,
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};
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static const struct watchdog_ops xilinx_wdt_ops = {
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.owner = THIS_MODULE,
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.start = xilinx_wdt_start,
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.stop = xilinx_wdt_stop,
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.ping = xilinx_wdt_keepalive,
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};
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static u32 xwdt_selftest(struct xwdt_device *xdev)
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{
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int i;
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u32 timer_value1;
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u32 timer_value2;
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spin_lock(&xdev->spinlock);
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timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
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timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
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for (i = 0;
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((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
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(timer_value2 == timer_value1)); i++) {
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timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
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}
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spin_unlock(&xdev->spinlock);
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if (timer_value2 != timer_value1)
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return ~XWT_TIMER_FAILED;
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else
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return XWT_TIMER_FAILED;
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}
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static int xwdt_probe(struct platform_device *pdev)
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{
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int rc;
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u32 pfreq = 0, enable_once = 0;
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struct resource *res;
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struct xwdt_device *xdev;
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struct watchdog_device *xilinx_wdt_wdd;
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xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
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if (!xdev)
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return -ENOMEM;
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xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
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xilinx_wdt_wdd->info = &xilinx_wdt_ident;
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xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
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xilinx_wdt_wdd->parent = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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xdev->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(xdev->base))
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return PTR_ERR(xdev->base);
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rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq);
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if (rc)
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dev_warn(&pdev->dev,
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"The watchdog clock frequency cannot be obtained\n");
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rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
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&xdev->wdt_interval);
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if (rc)
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dev_warn(&pdev->dev,
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"Parameter \"xlnx,wdt-interval\" not found\n");
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rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
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&enable_once);
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if (rc)
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dev_warn(&pdev->dev,
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"Parameter \"xlnx,wdt-enable-once\" not found\n");
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watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
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/*
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* Twice of the 2^wdt_interval / freq because the first wdt overflow is
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* ignored (interrupt), reset is only generated at second wdt overflow
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*/
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if (pfreq && xdev->wdt_interval)
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xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
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pfreq);
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spin_lock_init(&xdev->spinlock);
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watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
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rc = xwdt_selftest(xdev);
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if (rc == XWT_TIMER_FAILED) {
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dev_err(&pdev->dev, "SelfTest routine error\n");
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return rc;
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}
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rc = watchdog_register_device(xilinx_wdt_wdd);
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if (rc) {
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dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
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return rc;
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}
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dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
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xdev->base, xilinx_wdt_wdd->timeout);
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platform_set_drvdata(pdev, xdev);
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return 0;
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}
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static int xwdt_remove(struct platform_device *pdev)
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{
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struct xwdt_device *xdev = platform_get_drvdata(pdev);
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watchdog_unregister_device(&xdev->xilinx_wdt_wdd);
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return 0;
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}
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/* Match table for of_platform binding */
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static const struct of_device_id xwdt_of_match[] = {
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{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
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{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
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{},
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};
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MODULE_DEVICE_TABLE(of, xwdt_of_match);
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static struct platform_driver xwdt_driver = {
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.probe = xwdt_probe,
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.remove = xwdt_remove,
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.driver = {
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.owner = THIS_MODULE,
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.name = WATCHDOG_NAME,
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.of_match_table = xwdt_of_match,
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},
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};
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module_platform_driver(xwdt_driver);
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MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
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MODULE_DESCRIPTION("Xilinx Watchdog driver");
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MODULE_LICENSE("GPL v2");
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