linux-stable/drivers/clk/ingenic
Paul Cercueil 3024018bb2 clk: ingenic: Fix bugs with divided dividers
[ Upstream commit ed84ef1cd7 ]

Two fixes in one:

- In the "impose hardware constraints" block, the "logical" divider
  value (aka. not translated to the hardware) was clamped to fit in the
  register area, but this totally ignored the fact that the divider
  value can itself have a fixed divider.

- The code that made sure that the divider value returned by the
  function was a multiple of its own fixed divider could result in a
  wrong value being calculated, because it was rounded down instead of
  rounded up.

Fixes: 4afe2d1a6e ("clk: ingenic: Allow divider value to be divided")
Co-developed-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-11-25 09:48:32 +01:00
..
cgu.c clk: ingenic: Fix bugs with divided dividers 2021-11-25 09:48:32 +01:00
cgu.h clk: ingenic: Support overriding PLLs M/N/OD calc algorithm 2021-06-27 19:49:18 -07:00
jz4725b-cgu.c clk: Support bypassing dividers 2021-06-27 19:49:17 -07:00
jz4740-cgu.c clk: Support bypassing dividers 2021-06-27 19:49:17 -07:00
jz4760-cgu.c clk: ingenic: Add support for the JZ4760 2021-06-27 19:49:18 -07:00
jz4770-cgu.c clk: ingenic: Remove pll_info.no_bypass_bit 2021-06-27 19:49:17 -07:00
jz4780-cgu.c clk: JZ4780: Reformat the code to align it. 2020-07-27 18:18:14 -07:00
Kconfig clk: ingenic: Add support for the JZ4760 2021-06-27 19:49:18 -07:00
Makefile clk: ingenic: Add support for the JZ4760 2021-06-27 19:49:18 -07:00
pm.c clk: ingenic: Handle setting the Low-Power Mode bit 2019-06-25 15:43:15 -07:00
pm.h clk: ingenic: Handle setting the Low-Power Mode bit 2019-06-25 15:43:15 -07:00
tcu.c clk: ingenic: Add support for the JZ4760 2021-06-27 19:49:18 -07:00
x1000-cgu.c clk: X1000: Add support for calculat REFCLK of USB PHY. 2020-07-27 18:18:14 -07:00
x1830-cgu.c clk: Ingenic: Add RTC related clocks for Ingenic SoCs. 2020-07-27 18:17:52 -07:00