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![Daniel Lezcano](/assets/img/avatar_default.png)
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
191 lines
4 KiB
C
191 lines
4 KiB
C
/*
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* H8/300 16bit Timer driver
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*
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* Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
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*/
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TSTR 0
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#define TISRC 6
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#define TCR 0
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#define TCNT 2
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#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
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#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
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struct timer16_priv {
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struct clocksource cs;
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unsigned long total_cycles;
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void __iomem *mapbase;
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void __iomem *mapcommon;
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unsigned short cs_enabled;
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unsigned char enb;
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unsigned char ovf;
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unsigned char ovie;
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};
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static unsigned long timer16_get_counter(struct timer16_priv *p)
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{
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unsigned short v1, v2, v3;
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unsigned char o1, o2;
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o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
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/* Make sure the timer value is stable. Stolen from acpi_pm.c */
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do {
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o2 = o1;
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v1 = ioread16be(p->mapbase + TCNT);
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v2 = ioread16be(p->mapbase + TCNT);
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v3 = ioread16be(p->mapbase + TCNT);
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o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
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} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
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|| (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
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if (likely(!o1))
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return v2;
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else
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return v2 + 0x10000;
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}
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static irqreturn_t timer16_interrupt(int irq, void *dev_id)
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{
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struct timer16_priv *p = (struct timer16_priv *)dev_id;
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bclr(p->ovf, p->mapcommon + TISRC);
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p->total_cycles += 0x10000;
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return IRQ_HANDLED;
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}
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static inline struct timer16_priv *cs_to_priv(struct clocksource *cs)
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{
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return container_of(cs, struct timer16_priv, cs);
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}
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static u64 timer16_clocksource_read(struct clocksource *cs)
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{
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struct timer16_priv *p = cs_to_priv(cs);
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unsigned long raw, value;
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value = p->total_cycles;
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raw = timer16_get_counter(p);
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return value + raw;
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}
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static int timer16_enable(struct clocksource *cs)
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{
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struct timer16_priv *p = cs_to_priv(cs);
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WARN_ON(p->cs_enabled);
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p->total_cycles = 0;
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iowrite16be(0x0000, p->mapbase + TCNT);
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iowrite8(0x83, p->mapbase + TCR);
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bset(p->ovie, p->mapcommon + TISRC);
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bset(p->enb, p->mapcommon + TSTR);
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p->cs_enabled = true;
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return 0;
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}
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static void timer16_disable(struct clocksource *cs)
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{
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struct timer16_priv *p = cs_to_priv(cs);
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WARN_ON(!p->cs_enabled);
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bclr(p->ovie, p->mapcommon + TISRC);
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bclr(p->enb, p->mapcommon + TSTR);
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p->cs_enabled = false;
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}
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static struct timer16_priv timer16_priv = {
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.cs = {
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.name = "h8300_16timer",
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.rating = 200,
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.read = timer16_clocksource_read,
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.enable = timer16_enable,
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.disable = timer16_disable,
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.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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},
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};
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#define REG_CH 0
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#define REG_COMM 1
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static int __init h8300_16timer_init(struct device_node *node)
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{
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void __iomem *base[2];
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int ret, irq;
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unsigned int ch;
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struct clk *clk;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("failed to get clock for clocksource\n");
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return PTR_ERR(clk);
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}
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ret = -ENXIO;
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base[REG_CH] = of_iomap(node, 0);
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if (!base[REG_CH]) {
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pr_err("failed to map registers for clocksource\n");
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goto free_clk;
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}
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base[REG_COMM] = of_iomap(node, 1);
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if (!base[REG_COMM]) {
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pr_err("failed to map registers for clocksource\n");
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goto unmap_ch;
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}
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ret = -EINVAL;
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irq = irq_of_parse_and_map(node, 0);
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if (!irq) {
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pr_err("failed to get irq for clockevent\n");
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goto unmap_comm;
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}
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of_property_read_u32(node, "renesas,channel", &ch);
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timer16_priv.mapbase = base[REG_CH];
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timer16_priv.mapcommon = base[REG_COMM];
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timer16_priv.enb = ch;
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timer16_priv.ovf = ch;
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timer16_priv.ovie = 4 + ch;
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ret = request_irq(irq, timer16_interrupt,
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IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
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if (ret < 0) {
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pr_err("failed to request irq %d of clocksource\n", irq);
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goto unmap_comm;
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}
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clocksource_register_hz(&timer16_priv.cs,
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clk_get_rate(clk) / 8);
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return 0;
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unmap_comm:
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iounmap(base[REG_COMM]);
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unmap_ch:
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iounmap(base[REG_CH]);
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free_clk:
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clk_put(clk);
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return ret;
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}
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TIMER_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
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h8300_16timer_init);
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